LPC1769FBD100,551 NXP Semiconductors, LPC1769FBD100,551 Datasheet - Page 463

• Manufacturer Part Number: LPC1769FBD100,551
• Description: IC ARM CORTEX MCU 512K 100-LQFP
• Manufacturer: NXP Semiconductors
• Series: LPC17xxr

Specifications of LPC1769FBD100,551

• Program Memory Type: FLASH
• Program Memory Size: 512KB (512K x 8)
• Package / Case: 100-LQFP
• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 120MHz
• Connectivity: CAN, Ethernet, I²C, IrDA, Microwire, SPI, SSI, UART/USART, USB OTG
• Peripherals: Brown-out Detect/Reset, DMA, I²S, Motor Control PWM, POR, PWM, WDT
• Number Of I /o: 70
• Ram Size: 64K x 8
• Voltage - Supply (vcc/vdd): 2.4 V ~ 3.6 V
• Data Converters: A/D 8x12b, D/A 1x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Processor Series: LPC17
• Core: ARM Cortex M3
• Data Bus Width: 32 bit
• Data Ram Size: 64 KB
• Interface Type: Ethernet, USB, OTG, CAN
• Maximum Clock Frequency: 120 MHz
• Number Of Programmable I/os: 70
• Number Of Timers: 4
• Operating Supply Voltage: 3.3 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2, MCB1760, MCB1760U, MCB1760UME
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 12 bit, 8 Channel
• On-chip Dac: 10 bit
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 622-1005 - USB IN-CIRCUIT PROG ARM7 LPC2K
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 568-4966; 935290522551

NXP Semiconductors
UM10360
User manual
19.9.7.2 Data transfer after loss of arbitration
19.9.7.3 Forced access to the I
19.9.7.4 I
19.9.7.5 Bus error
If the I
a repeated START condition itself, it will release the bus, and no interrupt request is
generated. If another master frees the bus by generating a STOP condition, the I
will transmit a normal START condition (state 0x08), and a retry of the total serial data
transfer can commence.
Arbitration may be lost in the master transmitter and master receiver modes (see
Figure
0x78, and 0xB0 (see
If the STA flag in I2CON is set by the routines which service these states, then, if the bus
is free again, a START condition (state 0x08) is transmitted without intervention by the
CPU, and a retry of the total serial transfer can commence.
In some applications, it may be possible for an uncontrolled source to cause a bus
hang-up. In such situations, the problem may be caused by interference, temporary
interruption of the bus or a temporary short-circuit between SDA and SCL.
If an uncontrolled source generates a superfluous START or masks a STOP condition,
then the I
obtained within a reasonable amount of time, then a forced access to the I
possible. This is achieved by setting the STO flag while the STA flag is still set. No STOP
condition is transmitted. The I
and is able to transmit a START condition. The STO flag is cleared by hardware
Figure
An I
the bus. If the SCL line is obstructed (pulled LOW) by a device on the bus, no further serial
transfer is possible, and the problem must be resolved by the device that is pulling the
SCL bus line LOW.
Typically, the SDA line may be obstructed by another device on the bus that has become
out of synchronization with the current bus master by either missing a clock, or by sensing
a noise pulse as a clock. In this case, the problem can be solved by transmitting additional
clock pulses on the SCL line
timeout timer to detect an obstructed bus, but this can be implemented using another
timer in the system. When detected, software can force clocks (up to 9 may be required)
on SCL until SDA is released by the offending device. At that point, the slave may still be
out of synchronization, so a START should be generated to insure that all I
are synchronized.
A bus error occurs when a START or STOP condition is detected at an illegal position in
the format frame. Examples of illegal positions are during the serial transfer of an address
byte, a data bit, or an acknowledge bit.
2
C-bus obstructed by a LOW level on SCL or SDA
2
C-bus hang-up can occur if either the SDA or SCL line is held LOW by any device on
2
91). Loss of arbitration is indicated by the following states in I2STAT; 0x38, 0x68,
98.
C hardware detects a repeated START condition on the I
2
C-bus stays busy indefinitely. If the STA flag is set and bus access is not
All information provided in this document is subject to legal disclaimers.
Figure 93
Rev. 2 — 19 August 2010
2
C-bus
Figure
2
C hardware behaves as if a STOP condition was received
and
Figure
99. The I
94).
2
C interface does not include a dedicated
Chapter 19: LPC17xx I2C0/1/2
2
C-bus before generating
UM10360
© NXP B.V. 2010. All rights reserved.
2
2
C-bus is
C peripherals
2
463 of 840
C block