LPC1769FBD100,551 NXP Semiconductors, LPC1769FBD100,551 Datasheet - Page 619

• Manufacturer Part Number: LPC1769FBD100,551
• Description: IC ARM CORTEX MCU 512K 100-LQFP
• Manufacturer: NXP Semiconductors
• Series: LPC17xxr

Specifications of LPC1769FBD100,551

• Program Memory Type: FLASH
• Program Memory Size: 512KB (512K x 8)
• Package / Case: 100-LQFP
• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 120MHz
• Connectivity: CAN, Ethernet, I²C, IrDA, Microwire, SPI, SSI, UART/USART, USB OTG
• Peripherals: Brown-out Detect/Reset, DMA, I²S, Motor Control PWM, POR, PWM, WDT
• Number Of I /o: 70
• Ram Size: 64K x 8
• Voltage - Supply (vcc/vdd): 2.4 V ~ 3.6 V
• Data Converters: A/D 8x12b, D/A 1x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Processor Series: LPC17
• Core: ARM Cortex M3
• Data Bus Width: 32 bit
• Data Ram Size: 64 KB
• Interface Type: Ethernet, USB, OTG, CAN
• Maximum Clock Frequency: 120 MHz
• Number Of Programmable I/os: 70
• Number Of Timers: 4
• Operating Supply Voltage: 3.3 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2, MCB1760, MCB1760U, MCB1760UME
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 12 bit, 8 Channel
• On-chip Dac: 10 bit
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 622-1005 - USB IN-CIRCUIT PROG ARM7 LPC2K
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 568-4966; 935290522551

NXP Semiconductors
32.4 Boot process flowchart
UM10360
User manual
Fig 137. Boot process flowchart
(1) For details on handling the crystal frequency, see
(2) For details on available ISP commands based on the CRP settings see
CRP1/2/3 ENABLED?
USER CODE VALID?
CRP3 ENABLED?
WATCHDOG
FLAG SET?
INITIALIZE
RESET
A
yes
yes
yes
no
no
yes
no
no
All information provided in this document is subject to legal disclaimers.
no
Chapter 32: LPC17xx Flash memory interface and programming
RECEIVE CRYSTAL
RUN AUTO-BAUD
Rev. 2 — 19 August 2010
SUCCESSFUL?
FREQUENCY
(P2.10=LOW)
AUTO-BAUD
Enter ISP
ENABLE DEBUG
MODE?
Section 32.8.9 “Re-invoke ISP” on page 636
yes
yes
1
no
Section 32.6 “Code Read Protection (CRP)”
USER CODE
VALID?
RUN ISP COMMAND
HANDLER
EXECUTE INTERNAL
2
yes
USER CODE
A
UM10360
© NXP B.V. 2010. All rights reserved.
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