LPC1769FBD100,551 NXP Semiconductors, LPC1769FBD100,551 Datasheet - Page 30

• Manufacturer Part Number: LPC1769FBD100,551
• Description: IC ARM CORTEX MCU 512K 100-LQFP
• Manufacturer: NXP Semiconductors
• Series: LPC17xxr

Specifications of LPC1769FBD100,551

• Program Memory Type: FLASH
• Program Memory Size: 512KB (512K x 8)
• Package / Case: 100-LQFP
• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 120MHz
• Connectivity: CAN, Ethernet, I²C, IrDA, Microwire, SPI, SSI, UART/USART, USB OTG
• Peripherals: Brown-out Detect/Reset, DMA, I²S, Motor Control PWM, POR, PWM, WDT
• Number Of I /o: 70
• Ram Size: 64K x 8
• Voltage - Supply (vcc/vdd): 2.4 V ~ 3.6 V
• Data Converters: A/D 8x12b, D/A 1x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Processor Series: LPC17
• Core: ARM Cortex M3
• Data Bus Width: 32 bit
• Data Ram Size: 64 KB
• Interface Type: Ethernet, USB, OTG, CAN
• Maximum Clock Frequency: 120 MHz
• Number Of Programmable I/os: 70
• Number Of Timers: 4
• Operating Supply Voltage: 3.3 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2, MCB1760, MCB1760U, MCB1760UME
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 12 bit, 8 Channel
• On-chip Dac: 10 bit
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 622-1005 - USB IN-CIRCUIT PROG ARM7 LPC2K
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 568-4966; 935290522551

NXP Semiconductors
4.2 Register description
UM10360
User manual
All registers, regardless of size, are on word address boundaries. Details of the registers
appear in the description of each function.
Table 14.
Name
Clock source selection
CLKSRCSEL
Phase Locked Loop (PLL0, Main PLL)
PLL0CON
PLL0CFG
PLL0STAT
PLL0FEED
Phase Locked Loop (PLL1, USB PLL)
PLL1CON
PLL1CFG
PLL1STAT
PLL1FEED
Clock dividers
CCLKCFG
USBCLKCFG
PCLKSEL0
PCLKSEL1
Power control
PCON
PCONP
Utility
CLKOUTCFG
Summary of system control registers
PLL0 Control Register
Description
Clock Source Select Register
PLL0 Configuration Register
PLL0 Status Register
PLL0 Feed Register
PLL1 Control Register
PLL1 Configuration Register
PLL1 Status Register
PLL1 Feed Register
CPU Clock Configuration Register
USB Clock Configuration Register
Peripheral Clock Selection register 0.
Peripheral Clock Selection register 1.
Power Control Register
Power Control for Peripherals Register
Clock Output Configuration Register
All information provided in this document is subject to legal disclaimers.
Rev. 2 — 19 August 2010
Chapter 4: LPC17xx Clocking and power control
Access
R/W
R/W
R/W
RO
WO
R/W
R/W
RO
WO
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Reset value Address
0
0
0
0
NA
0
0
0
NA
0
0
0
0
0
0x03BE
0
UM10360
© NXP B.V. 2010. All rights reserved.
0x400F C080
0x400F C084
0x400F C104
0x400F C0C4
0x400F C1C8
0x400F C10C
0x400F C088
0x400F C08C
0x400F C0A0
0x400F C0A4
0x400F C0A8
0x400F C0AC
0x400F C108
0x400F C1A8
0x400F C1AC
0x400F C0C0
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