LPC1769FBD100,551 NXP Semiconductors, LPC1769FBD100,551 Datasheet - Page 526

• Manufacturer Part Number: LPC1769FBD100,551
• Description: IC ARM CORTEX MCU 512K 100-LQFP
• Manufacturer: NXP Semiconductors
• Series: LPC17xxr

Specifications of LPC1769FBD100,551

• Program Memory Type: FLASH
• Program Memory Size: 512KB (512K x 8)
• Package / Case: 100-LQFP
• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 120MHz
• Connectivity: CAN, Ethernet, I²C, IrDA, Microwire, SPI, SSI, UART/USART, USB OTG
• Peripherals: Brown-out Detect/Reset, DMA, I²S, Motor Control PWM, POR, PWM, WDT
• Number Of I /o: 70
• Ram Size: 64K x 8
• Voltage - Supply (vcc/vdd): 2.4 V ~ 3.6 V
• Data Converters: A/D 8x12b, D/A 1x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Processor Series: LPC17
• Core: ARM Cortex M3
• Data Bus Width: 32 bit
• Data Ram Size: 64 KB
• Interface Type: Ethernet, USB, OTG, CAN
• Maximum Clock Frequency: 120 MHz
• Number Of Programmable I/os: 70
• Number Of Timers: 4
• Operating Supply Voltage: 3.3 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2, MCB1760, MCB1760U, MCB1760UME
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 12 bit, 8 Channel
• On-chip Dac: 10 bit
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 622-1005 - USB IN-CIRCUIT PROG ARM7 LPC2K
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 568-4966; 935290522551

NXP Semiconductors
Table 455. MCPWM Control read address (MCCON - 0x400B 8000) bit description
UM10360
User manual
Bit
0
1
2
3
4
7:5
8
9
10
11
12
Symbol
RUN0
CENTER0
POLA0
DTE0
DISUP0
-
RUN1
CENTER1
POLA1
DTE1
DISUP1
25.7.1.1 MCPWM Control read address (MCCON - 0x400B 8000)
25.7.1 MCPWM Control register
Value Description
0
1
0
1
0
1
0
1
0
1
-
0
1
0
1
0
1
0
1
0
1
The MCCON register controls the operation of all channels of the PWM. This address is
read-only, but the underlying register can be modified by writing to addresses
MCCON_SET and MCCON_CLR.
Stops/starts timer channel 0.
Stop.
Run.
Edge/center aligned operation for channel 0.
Edge-aligned.
Center-aligned.
Selects polarity of the MCOA0 and MCOB0 pins.
Passive state is LOW, active state is HIGH.
Passive state is HIGH, active state is LOW.
Controls the dead-time feature for channel 0.
Dead-time disabled.
Dead-time enabled.
Enable/disable updates of functional registers for channel 0 (see
Section
Functional registers are updated from the write registers at the end of each PWM
cycle.
Functional registers remain the same as long as the timer is running.
Reserved.
Stops/starts timer channel 1.
Stop.
Run.
Edge/center aligned operation for channel 1.
Edge-aligned.
Center-aligned.
Selects polarity of the MCOA1 and MCOB1 pins.
Passive state is LOW, active state is HIGH.
Passive state is HIGH, active state is LOW.
Controls the dead-time feature for channel 1.
Dead-time disabled.
Dead-time enabled.
Enable/disable updates of functional registers for channel 1 (see
Section
Functional registers are updated from the write registers at the end of each PWM
cycle.
Functional registers remain the same as long as the timer is running.
25.7.6.1).
25.7.6.1).
All information provided in this document is subject to legal disclaimers.
Rev. 2 — 19 August 2010
Chapter 25: LPC17xx Motor control PWM
Section
Section
UM10360
© NXP B.V. 2010. All rights reserved.
25.8.2,
25.8.2,
526 of 840
Reset
value
0
0
0
0
0
0
0
0
0
0