LPC1769FBD100,551 NXP Semiconductors, LPC1769FBD100,551 Datasheet - Page 503
![IC ARM CORTEX MCU 512K 100-LQFP](/photos/6/65/66516/568-100-lqfp_sot407-1_sml.jpg)
LPC1769FBD100,551
Manufacturer Part Number
LPC1769FBD100,551
Description
IC ARM CORTEX MCU 512K 100-LQFP
Manufacturer
NXP Semiconductors
Series
LPC17xxr
Datasheets
1.OM11043.pdf
(79 pages)
2.LPC1767FBD100551.pdf
(2 pages)
3.LPC1767FBD100551.pdf
(840 pages)
4.LPC1769FBD100551.pdf
(66 pages)
Specifications of LPC1769FBD100,551
Program Memory Type
FLASH
Program Memory Size
512KB (512K x 8)
Package / Case
100-LQFP
Core Processor
ARM® Cortex-M3™
Core Size
32-Bit
Speed
120MHz
Connectivity
CAN, Ethernet, I²C, IrDA, Microwire, SPI, SSI, UART/USART, USB OTG
Peripherals
Brown-out Detect/Reset, DMA, I²S, Motor Control PWM, POR, PWM, WDT
Number Of I /o
70
Ram Size
64K x 8
Voltage - Supply (vcc/vdd)
2.4 V ~ 3.6 V
Data Converters
A/D 8x12b, D/A 1x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Processor Series
LPC17
Core
ARM Cortex M3
Data Bus Width
32 bit
Data Ram Size
64 KB
Interface Type
Ethernet, USB, OTG, CAN
Maximum Clock Frequency
120 MHz
Number Of Programmable I/os
70
Number Of Timers
4
Operating Supply Voltage
3.3 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
MDK-ARM, RL-ARM, ULINK2, MCB1760, MCB1760U, MCB1760UME
Minimum Operating Temperature
- 40 C
On-chip Adc
12 bit, 8 Channel
On-chip Dac
10 bit
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
622-1005 - USB IN-CIRCUIT PROG ARM7 LPC2K
Eeprom Size
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Other names
568-4966
935290522551
935290522551
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
LPC1769FBD100,551
Manufacturer:
NXP Semiconductors
Quantity:
10 000
- OM11043 PDF datasheet
- LPC1767FBD100551 PDF datasheet #2
- LPC1767FBD100551 PDF datasheet #3
- LPC1769FBD100551 PDF datasheet #4
- Current page: 503 of 840
- Download datasheet (6Mb)
NXP Semiconductors
UM10360
User manual
Counting can be halted in software by writing a ‘0’ to the Enable_Timer bit - RICTRL(2).
Counting will also be halted when the processor is halted for debugging provided the
Enable_Break bit – RICTRL(1) is set. Both the Enable_Timer and Enable_Break bits are
set on reset.
The interrupt flag can be cleared in software by writing a ‘1’ to the Interrupt bit –
RICTRL(0).
Software can load the counter to any value at any time by writing to RICOUNTER.
The counter (RICOUNTER), RICOMPVAL register, RIMASK register and RICTRL register
can all be read by software at any time.
Fig 117. RI timer block diagram
RESET
CLR
SET
COMPARE REGISTER
32-bit COUNTER
COMPARATOR
PBUS
PBUS
32
32
All information provided in this document is subject to legal disclaimers.
PBUS
PBUS
ENA
EQ
Rev. 2 — 19 August 2010
CLR
Chapter 22: LPC17xx Repetitive Interrupt Timer (RIT)
RESET
MASK REGISTER
32
PBUS
32
ENABLE_CLK
PBUS
write '1' to
PBUS
RESET
RESET
RESET
SET_INT
PBUS
PBUS
clear
CNT_ENA
register
S
C
CTRL
SET
CLR
CLR
3
2
0
ENABLE_BREAK
ENABLE_TIMER
UM10360
BREAK
© NXP B.V. 2010. All rights reserved.
OperatingSystemTimer
INTR
PBUS
503 of 840
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