LPC1769FBD100,551 NXP Semiconductors, LPC1769FBD100,551 Datasheet - Page 795

• Manufacturer Part Number: LPC1769FBD100,551
• Description: IC ARM CORTEX MCU 512K 100-LQFP
• Manufacturer: NXP Semiconductors
• Series: LPC17xxr

Specifications of LPC1769FBD100,551

• Program Memory Type: FLASH
• Program Memory Size: 512KB (512K x 8)
• Package / Case: 100-LQFP
• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 120MHz
• Connectivity: CAN, Ethernet, I²C, IrDA, Microwire, SPI, SSI, UART/USART, USB OTG
• Peripherals: Brown-out Detect/Reset, DMA, I²S, Motor Control PWM, POR, PWM, WDT
• Number Of I /o: 70
• Ram Size: 64K x 8
• Voltage - Supply (vcc/vdd): 2.4 V ~ 3.6 V
• Data Converters: A/D 8x12b, D/A 1x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Processor Series: LPC17
• Core: ARM Cortex M3
• Data Bus Width: 32 bit
• Data Ram Size: 64 KB
• Interface Type: Ethernet, USB, OTG, CAN
• Maximum Clock Frequency: 120 MHz
• Number Of Programmable I/os: 70
• Number Of Timers: 4
• Operating Supply Voltage: 3.3 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2, MCB1760, MCB1760U, MCB1760UME
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 12 bit, 8 Channel
• On-chip Dac: 10 bit
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 622-1005 - USB IN-CIRCUIT PROG ARM7 LPC2K
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 568-4966; 935290522551

NXP Semiconductors
UM10360
User manual
34.4.5.8.3 Subregions
Use an STM instruction to optimize this:
; R1 = region number
; R2 = address
; R3 = size, attributes in one
LDR R0, =MPU_RNR
STM R0, {R1-R3}
You can do this in two words for pre-packed information. This means that the RBAR
contains the required region number and had the VALID bit set to 1, see
this when the data is statically packed, for example in a boot loader:
; R1 = address and region number in one
; R2 = size and attributes in one
LDR R0, =MPU_RBAR
STR R1, [R0, #0x0] ; Region base address and
STR R2, [R0, #0x4] ; Region Attribute, Size and Enable
Use an STM instruction to optimize this:
; R1 = address and region number in one
; R2 = size and attributes in one
LDR R0,=MPU_RBAR
STM R0, {R1-R2}
Regions of 256 bytes or more are divided into eight equal-sized subregions. Set the
corresponding bit in the SRD field of the RASR to disable a subregion, see
least significant bit of SRD controls the first subregion, and the most significant bit controls
the last subregion. Disabling a subregion means another region overlapping the disabled
range matches instead. If no other enabled region overlaps the disabled subregion the
MPU issues a fault.
Regions of 32, 64, and 128 bytes do not support subregions, With regions of these sizes,
you must set the SRD field to 0x00, otherwise the MPU behavior is Unpredictable.
Example of SRD use:
128KB, and region two is 512KB. To ensure the attributes from region one apply to the
first128KB region, set the SRD field for region two to b00000011 to disable the first two
subregions, as the figure shows.
All information provided in this document is subject to legal disclaimers.
; region number combined with VALID (bit 4) set to 1
; and Region Attribute, Size and Enable
; 0xE000ED98, MPU region number register
; Region Number, address, attribute, size and enable
; 0xE000ED9C, MPU Region Base register
; 0xE000ED9C, MPU Region Base register
; Region base address, region number and VALID bit,
Rev. 2 — 19 August 2010
Two regions with the same base address overlap. Region one is
Chapter 34: Appendix: Cortex-M3 user guide
UM10360
© NXP B.V. 2010. All rights reserved.
Table
Table
684. Use
685. The
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