LPC1769FBD100,551 NXP Semiconductors, LPC1769FBD100,551 Datasheet - Page 540

• Manufacturer Part Number: LPC1769FBD100,551
• Description: IC ARM CORTEX MCU 512K 100-LQFP
• Manufacturer: NXP Semiconductors
• Series: LPC17xxr

Specifications of LPC1769FBD100,551

• Program Memory Type: FLASH
• Program Memory Size: 512KB (512K x 8)
• Package / Case: 100-LQFP
• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 120MHz
• Connectivity: CAN, Ethernet, I²C, IrDA, Microwire, SPI, SSI, UART/USART, USB OTG
• Peripherals: Brown-out Detect/Reset, DMA, I²S, Motor Control PWM, POR, PWM, WDT
• Number Of I /o: 70
• Ram Size: 64K x 8
• Voltage - Supply (vcc/vdd): 2.4 V ~ 3.6 V
• Data Converters: A/D 8x12b, D/A 1x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Processor Series: LPC17
• Core: ARM Cortex M3
• Data Bus Width: 32 bit
• Data Ram Size: 64 KB
• Interface Type: Ethernet, USB, OTG, CAN
• Maximum Clock Frequency: 120 MHz
• Number Of Programmable I/os: 70
• Number Of Timers: 4
• Operating Supply Voltage: 3.3 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2, MCB1760, MCB1760U, MCB1760UME
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 12 bit, 8 Channel
• On-chip Dac: 10 bit
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 622-1005 - USB IN-CIRCUIT PROG ARM7 LPC2K
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 568-4966; 935290522551

NXP Semiconductors
UM10360
User manual
25.8.5 External event counting (Counter mode)
25.8.6 Three-phase DC mode
If a channel’s HNF bit in the MCCAPCON register is set to enable “noise filtering”, a
selected edge on an MCI pin starts the dead-time counter for that channel, and the
capture event actions described below are delayed until the dead-time counter reaches 0.
This function is targeted specifically for performing three-phase brushless DC motor
control with Hall sensors.
A capture event on a channel (possibly delayed by HNF) causes the following:
If a channel’s MODE bit is 1 in MCCNTCON, its TC is incremented by rising and/or falling
edge(s) (synchronously detected) on the MCI0-2 input(s), rather than by PCLK. The PWM
functions and capture functions are unaffected.
The three-phase DC mode is selected by setting the DCMODE bit in the MCCON register.
In this mode, the internal MCOA0 signal can be routed to any or all of the MCO outputs.
Each MCO output is masked by a bit in the current Commutation Pattern register MCCP. If
a bit in the MCCP register is 0, its output pin has the logic level for the passive state of
output MCOA0. The polarity of the off state is determined by the POLA0 bit.
All MCO outputs that have 1 bits in the MCCP register are controlled by the internal
MCOA0 signal.
The three MCOB output pins are inverted when the INVBDC bit is 1 in the MCCON
register. This feature accommodates bridge-drivers that have active-low inputs for the
low-side switches.
The MCCP register is implemented as a shadow register pair, so that changes to the
active commutation pattern occur at the beginning of a new PWM cycle. See
25.8.2
Figure 126
and 3 in the MCCP register (corresponding to outputs MCOB1 and MCOB0) are set to 0
so that these outputs are masked and in the off state. Their logic level is determined by
the POLA0 bit (here, POLA0 = 0 so the passive state is logic LOW). The INVBDC bit is set
to 0 (logic level not inverted) so that the B output have the same polarity as the A outputs.
Note that this mode differs from other modes in that the MCOB outputs are not the
opposite of the MCOA outputs.
In the situation shown in
That means that MCOA1 and both MCO outputs for channel 2 follow the MCOA0 signal.
•
•
•
The current value of the TC is stored in the Capture register (CAP).
If the channel’s capture event interrupt is enabled (see
interrupt flag is set.
If the channel’s RT bit is set in the MCCAPCON register, enabling reset on a capture
event, the input event has the same effect as matching the channel’s TC to its LIM
register. This includes resetting the TC and switching the MCO pin(s) in edge-aligned
mode as described in
for more about writing and reading such registers.
shows sample waveforms of the MCO outputs in three-phase DC mode. Bits 1
All information provided in this document is subject to legal disclaimers.
Rev. 2 — 19 August 2010
Figure
25.7.6
126, bits 0, 2, 4, and 5 in the MCCP register are set to 1.
and 25.8.1.
Chapter 25: LPC17xx Motor control PWM
Table
463), the capture event
UM10360
© NXP B.V. 2010. All rights reserved.
25.7.6
540 of 840
and