LPC1769FBD100,551 NXP Semiconductors, LPC1769FBD100,551 Datasheet - Page 347

• Manufacturer Part Number: LPC1769FBD100,551
• Description: IC ARM CORTEX MCU 512K 100-LQFP
• Manufacturer: NXP Semiconductors
• Series: LPC17xxr

Specifications of LPC1769FBD100,551

• Program Memory Type: FLASH
• Program Memory Size: 512KB (512K x 8)
• Package / Case: 100-LQFP
• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 120MHz
• Connectivity: CAN, Ethernet, I²C, IrDA, Microwire, SPI, SSI, UART/USART, USB OTG
• Peripherals: Brown-out Detect/Reset, DMA, I²S, Motor Control PWM, POR, PWM, WDT
• Number Of I /o: 70
• Ram Size: 64K x 8
• Voltage - Supply (vcc/vdd): 2.4 V ~ 3.6 V
• Data Converters: A/D 8x12b, D/A 1x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Processor Series: LPC17
• Core: ARM Cortex M3
• Data Bus Width: 32 bit
• Data Ram Size: 64 KB
• Interface Type: Ethernet, USB, OTG, CAN
• Maximum Clock Frequency: 120 MHz
• Number Of Programmable I/os: 70
• Number Of Timers: 4
• Operating Supply Voltage: 3.3 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2, MCB1760, MCB1760U, MCB1760UME
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 12 bit, 8 Channel
• On-chip Dac: 10 bit
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 622-1005 - USB IN-CIRCUIT PROG ARM7 LPC2K
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 568-4966; 935290522551

NXP Semiconductors
UM10360
User manual
Fig 55. Receive buffer layout for standard and extended frame format configurations
31
31
RX
RX
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16.5.5 Error Management Logic (EML)
16.5.6 Bit Timing Logic (BTL)
16.5.7 Bit Stream Processor (BSP)
16.5.8 CAN controller self-tests
RX Data 4
RX Data 8
RX Data 4
RX Data 8
Frame info
Frame info
ID.28
The EML is responsible for the error confinement. It gets error announcements from the
BSP and then informs the BSP and IML about error statistics.
The Bit Timing Logic monitors the serial CAN Bus line and handles the Bus line related bit
timing. It synchronizes to the bit stream on the CAN Bus on a "recessive" to "dominant"
Bus line transition at the beginning of a message (hard synchronization) and
re-synchronizes on further transitions during the reception of a message (soft
synchronization). The BTL also provides programmable time segments to compensate for
the propagation delay times and phase shifts (e.g. due to oscillator drifts) and to define the
sample point and the number of samples to be taken within a bit time.
The Bit Stream Processor is a sequencer, controlling the data stream between the
Transmit Buffer, Receive Buffers and the CAN Bus. It also performs the error detection,
arbitration, stuffing and error handling on the CAN Bus.
The CAN controller supports two different options for self-tests:
•
•
24 23
24 23
Global Self-Test (setting the self reception request bit in normal Operating Mode)
Local Self-Test (setting the self reception request bit in Self Test Mode)
unused
unused
unused
RX Data 3
RX Data 7
RX Data 3
RX Data 7
RX DLC
RX DLC
All information provided in this document is subject to legal disclaimers.
Extended Frame Format (29-bit Identifier)
Standard Frame Format (11-bit Identifier)
16 15
16 15
...
Rev. 2 — 19 August 2010
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unused
RX Data 2
RX Data 6
RX Data 2
RX Data 6
10 9 8 7
10 9 8 7
ID.28 ... ID.18
ID Index
ID Index
RX Data 1
RX Data 5
RX Data 1
RX Data 5
ID.00
0
0
RDA
RDB
RDA
RDB
RFS
RFS
RID
RID
Chapter 16: LPC17xx CAN1/2
BPM=bypass
message
Descriptor
Data Field
Descriptor
Data Field
Field
Field
UM10360
© NXP B.V. 2010. All rights reserved.
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