LPC1769FBD100,551 NXP Semiconductors, LPC1769FBD100,551 Datasheet - Page 497

• Manufacturer Part Number: LPC1769FBD100,551
• Description: IC ARM CORTEX MCU 512K 100-LQFP
• Manufacturer: NXP Semiconductors
• Series: LPC17xxr

Specifications of LPC1769FBD100,551

• Program Memory Type: FLASH
• Program Memory Size: 512KB (512K x 8)
• Package / Case: 100-LQFP
• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 120MHz
• Connectivity: CAN, Ethernet, I²C, IrDA, Microwire, SPI, SSI, UART/USART, USB OTG
• Peripherals: Brown-out Detect/Reset, DMA, I²S, Motor Control PWM, POR, PWM, WDT
• Number Of I /o: 70
• Ram Size: 64K x 8
• Voltage - Supply (vcc/vdd): 2.4 V ~ 3.6 V
• Data Converters: A/D 8x12b, D/A 1x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Processor Series: LPC17
• Core: ARM Cortex M3
• Data Bus Width: 32 bit
• Data Ram Size: 64 KB
• Interface Type: Ethernet, USB, OTG, CAN
• Maximum Clock Frequency: 120 MHz
• Number Of Programmable I/os: 70
• Number Of Timers: 4
• Operating Supply Voltage: 3.3 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2, MCB1760, MCB1760U, MCB1760UME
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 12 bit, 8 Channel
• On-chip Dac: 10 bit
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 622-1005 - USB IN-CIRCUIT PROG ARM7 LPC2K
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 568-4966; 935290522551

NXP Semiconductors
Table 430. Capture Control Register (T[0/1/2/3]CCR - addresses 0x4000 4028, 0x4000 8020, 0x4009 0028,
UM10360
User manual
Bit
0
1
2
3
4
5
31:6
Symbol
CAP0RE 1
CAP0FE 1
CAP0I
CAP1RE 1
CAP1FE 1
CAP1I
-
0x4009 4028) bit description
21.6.10 Capture Control Register (T[0/1/2/3]CCR - 0x4000 4028, 0x4000 8028,
21.6.11 External Match Register (T[0/1/2/3]EMR - 0x4000 403C, 0x4000 803C,
21.6.9 Capture Registers (CR0 - CR1)
Value Description
0
0
1
0
0
0
1
0
Each Capture register is associated with a device pin and may be loaded with the Timer
Counter value when a specified event occurs on that pin. The settings in the Capture
Control Register register determine whether the capture function is enabled, and whether
a capture event happens on the rising edge of the associated pin, the falling edge, or on
both edges.
0x4009 0028, 0x4009 4028)
The Capture Control Register is used to control whether one of the four Capture Registers
is loaded with the value in the Timer Counter when the capture event occurs, and whether
an interrupt is generated by the capture event. Setting both the rising and falling bits at the
same time is a valid configuration, resulting in a capture event for both edges. In the
description below, "n" represents the Timer number, 0 or 1.
Note: If Counter mode is selected for a particular CAP input in the CTCR, the 3 bits for
that input in this register should be programmed as 000, but capture and/or interrupt can
be selected for the other 3 CAP inputs.
0x4009 003C, 0x4009 403C)
The External Match Register provides both control and status of the external match pins.
In the descriptions below, “n” represents the Timer number, 0 or 1, and “m” represent a
Match number, 0 through 3.
Capture on CAPn.0 rising edge: a sequence of 0 then 1 on CAPn.0 will cause CR0 to be
loaded with the contents of TC.
This feature is disabled.
Capture on CAPn.0 falling edge: a sequence of 1 then 0 on CAPn.0 will cause CR0 to be
loaded with the contents of TC.
This feature is disabled.
Interrupt on CAPn.0 event: a CR0 load due to a CAPn.0 event will generate an interrupt.
This feature is disabled.
Capture on CAPn.1 rising edge: a sequence of 0 then 1 on CAPn.1 will cause CR1 to be
loaded with the contents of TC.
This feature is disabled.
Capture on CAPn.1 falling edge: a sequence of 1 then 0 on CAPn.1 will cause CR1 to be
loaded with the contents of TC.
This feature is disabled.
Interrupt on CAPn.1 event: a CR1 load due to a CAPn.1 event will generate an interrupt.
This feature is disabled.
Reserved, user software should not write ones to reserved bits. The value read from a
reserved bit is not defined.
All information provided in this document is subject to legal disclaimers.
Rev. 2 — 19 August 2010
Chapter 21: LPC17xx Timer 0/1/2/3
UM10360
© NXP B.V. 2010. All rights reserved.
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Reset
Value
0
0
0
0
0
0
NA