LPC1769FBD100,551 NXP Semiconductors, LPC1769FBD100,551 Datasheet - Page 214

• Manufacturer Part Number: LPC1769FBD100,551
• Description: IC ARM CORTEX MCU 512K 100-LQFP
• Manufacturer: NXP Semiconductors
• Series: LPC17xxr

Specifications of LPC1769FBD100,551

• Program Memory Type: FLASH
• Program Memory Size: 512KB (512K x 8)
• Package / Case: 100-LQFP
• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 120MHz
• Connectivity: CAN, Ethernet, I²C, IrDA, Microwire, SPI, SSI, UART/USART, USB OTG
• Peripherals: Brown-out Detect/Reset, DMA, I²S, Motor Control PWM, POR, PWM, WDT
• Number Of I /o: 70
• Ram Size: 64K x 8
• Voltage - Supply (vcc/vdd): 2.4 V ~ 3.6 V
• Data Converters: A/D 8x12b, D/A 1x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Processor Series: LPC17
• Core: ARM Cortex M3
• Data Bus Width: 32 bit
• Data Ram Size: 64 KB
• Interface Type: Ethernet, USB, OTG, CAN
• Maximum Clock Frequency: 120 MHz
• Number Of Programmable I/os: 70
• Number Of Timers: 4
• Operating Supply Voltage: 3.3 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2, MCB1760, MCB1760U, MCB1760UME
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 12 bit, 8 Channel
• On-chip Dac: 10 bit
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 622-1005 - USB IN-CIRCUIT PROG ARM7 LPC2K
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 568-4966; 935290522551

NXP Semiconductors
11.4 Features
11.5 Fixed endpoint configuration
UM10360
User manual
Table 184. USB related acronyms, abbreviations, and definitions used in this chapter
Table 185
configured at run time using the Endpoint realization registers, documented in
Section 11.10.4 “Endpoint realization
Acronym/abbreviation Description
AHB
ATLE
ATX
DD
DDP
DMA
EOP
EP
EP_RAM
FS
LED
LS
MPS
NAK
PLL
RAM
SOF
SIE
SRAM
UDCA
USB
•
•
•
•
•
•
•
•
•
Fully compliant with the USB 2.0 specification (full speed).
Supports 32 physical (16 logical) endpoints.
Supports Control, Bulk, Interrupt and Isochronous endpoints.
Scalable realization of endpoints at run time.
Endpoint maximum packet size selection (up to USB maximum specification) by
software at run time.
Supports SoftConnect and GoodLink features.
Supports DMA transfers on all non-control endpoints.
Allows dynamic switching between CPU controlled and DMA modes.
Double buffer implementation for Bulk and Isochronous endpoints.
shows the supported endpoint configurations. Endpoints are realized and
All information provided in this document is subject to legal disclaimers.
Rev. 2 — 19 August 2010
Advanced High-performance bus
Auto Transfer Length Extraction
Analog Transceiver
DMA Descriptor
DMA Description Pointer
Direct Memory Access
End-Of-Packet
Endpoint
Endpoint RAM
Full Speed
Light Emitting Diode
Low Speed
Maximum Packet Size
Negative Acknowledge
Phase Locked Loop
Random Access Memory
Start-Of-Frame
Serial Interface Engine
Synchronous RAM
USB Device Communication Area
Universal Serial Bus
registers”.
Chapter 11: LPC17xx USB device controller
UM10360
© NXP B.V. 2010. All rights reserved.
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