LPC1769FBD100,551 NXP Semiconductors, LPC1769FBD100,551 Datasheet - Page 516

• Manufacturer Part Number: LPC1769FBD100,551
• Description: IC ARM CORTEX MCU 512K 100-LQFP
• Manufacturer: NXP Semiconductors
• Series: LPC17xxr

Specifications of LPC1769FBD100,551

• Program Memory Type: FLASH
• Program Memory Size: 512KB (512K x 8)
• Package / Case: 100-LQFP
• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 120MHz
• Connectivity: CAN, Ethernet, I²C, IrDA, Microwire, SPI, SSI, UART/USART, USB OTG
• Peripherals: Brown-out Detect/Reset, DMA, I²S, Motor Control PWM, POR, PWM, WDT
• Number Of I /o: 70
• Ram Size: 64K x 8
• Voltage - Supply (vcc/vdd): 2.4 V ~ 3.6 V
• Data Converters: A/D 8x12b, D/A 1x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Processor Series: LPC17
• Core: ARM Cortex M3
• Data Bus Width: 32 bit
• Data Ram Size: 64 KB
• Interface Type: Ethernet, USB, OTG, CAN
• Maximum Clock Frequency: 120 MHz
• Number Of Programmable I/os: 70
• Number Of Timers: 4
• Operating Supply Voltage: 3.3 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2, MCB1760, MCB1760U, MCB1760UME
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 12 bit, 8 Channel
• On-chip Dac: 10 bit
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 622-1005 - USB IN-CIRCUIT PROG ARM7 LPC2K
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 568-4966; 935290522551

NXP Semiconductors
Table 447. PWM Timer Control Register (PWM1TCR address 0x4001 8004) bit description
Table 448. PWM Count control Register (PWM1CTCR - address 0x4001 8070) bit description
UM10360
User manual
Bit
0
1
2
3
31:4 -
Bit
1:0
3:2
31:4 -
Symbol
Counter Enable
Counter Reset
-
PWM Enable
Symbol
Counter/
Timer Mode
Count Input
Select
24.6.2 PWM Timer Control Register (PWM1TCR 0x4001 8004)
24.6.3 PWM Count Control Register (PWM1CTCR - 0x4001 8070)
Value Description
00
01
10
11
00
01
The PWM Timer Control Register (PWMTCR) is used to control the operation of the PWM
Timer Counter. The function of each of the bits is shown in
The Count Control Register (CTCR) is used to select between Timer and Counter mode,
and in Counter mode to select the pin and edge(s) for counting. The function of each of
the bits is shown in
Value Description
1
0
1
0
1
0
Timer Mode: the TC is incremented when the Prescale Counter matches the Prescale
Register.
Counter Mode: the TC is incremented on rising edges of the PCAP input selected by
bits 3:2.
Counter Mode: the TC is incremented on falling edges of the PCAP input selected by
bits 3:2.
Counter Mode: the TC is incremented on both edges of the PCAP input selected by
bits 3:2.
When bits 1:0 of this register are not 00, these bits select which PCAP pin which
carries the signal used to increment the TC.
PCAP1.0
PCAP1.1 (Other combinations are reserved)
Reserved, user software should not write ones to reserved bits. The value read from a
reserved bit is not defined.
The PWM Timer Counter and PWM Prescale Counter are enabled for counting.
The counters are disabled.
The PWM Timer Counter and the PWM Prescale Counter are synchronously reset
on the next positive edge of PCLK. The counters remain reset until this bit is
returned to zero.
Clear reset.
Reserved, user software should not write ones to reserved bits. The value read
from a reserved bit is not defined.
PWM mode is enabled (counter resets to 1). PWM mode causes the shadow
registers to operate in connection with the Match registers. A program write to a
Match register will not have an effect on the Match result until the corresponding bit
in PWMLER has been set, followed by the occurrence of a PWM Match 0 event.
Note that the PWM Match register that determines the PWM rate (PWM Match
Register 0 - MR0) must be set up prior to the PWM being enabled. Otherwise a
Match event will not occur to cause shadow register contents to become effective.
Timer mode is enabled (counter resets to 0).
Reserved, user software should not write ones to reserved bits. The value read
from a reserved bit is not defined.
All information provided in this document is subject to legal disclaimers.
Table
Rev. 2 — 19 August 2010
448.
Chapter 24: LPC17xx Pulse Width Modulator (PWM)
Table
447.
UM10360
© NXP B.V. 2010. All rights reserved.
516 of 840
Reset
Value
0
0
NA
0
NA
Reset
Value
00
00
NA