LPC1769FBD100,551 NXP Semiconductors, LPC1769FBD100,551 Datasheet - Page 746

• Manufacturer Part Number: LPC1769FBD100,551
• Description: IC ARM CORTEX MCU 512K 100-LQFP
• Manufacturer: NXP Semiconductors
• Series: LPC17xxr

Specifications of LPC1769FBD100,551

• Program Memory Type: FLASH
• Program Memory Size: 512KB (512K x 8)
• Package / Case: 100-LQFP
• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 120MHz
• Connectivity: CAN, Ethernet, I²C, IrDA, Microwire, SPI, SSI, UART/USART, USB OTG
• Peripherals: Brown-out Detect/Reset, DMA, I²S, Motor Control PWM, POR, PWM, WDT
• Number Of I /o: 70
• Ram Size: 64K x 8
• Voltage - Supply (vcc/vdd): 2.4 V ~ 3.6 V
• Data Converters: A/D 8x12b, D/A 1x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Processor Series: LPC17
• Core: ARM Cortex M3
• Data Bus Width: 32 bit
• Data Ram Size: 64 KB
• Interface Type: Ethernet, USB, OTG, CAN
• Maximum Clock Frequency: 120 MHz
• Number Of Programmable I/os: 70
• Number Of Timers: 4
• Operating Supply Voltage: 3.3 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2, MCB1760, MCB1760U, MCB1760UME
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 12 bit, 8 Channel
• On-chip Dac: 10 bit
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 622-1005 - USB IN-CIRCUIT PROG ARM7 LPC2K
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 568-4966; 935290522551

NXP Semiconductors
Table 639.
UM10360
User manual
Exception
number
1
2
3
4
[1]
Properties of the different exception types
IRQ
number
-
-14
-13
-12
[1]
•
•
•
•
•
•
A memory management fault is an exception that occurs because of a memory
protection related fault. The MPU or the fixed memory protection constraints
determines this fault, for both instruction and data memory transactions. This fault is
used to abort instruction accesses to Execute Never (XN) memory regions, even if
the MPU is disabled.
Bus fault
A bus fault is an exception that occurs because of a memory related fault for an
instruction or data memory transaction. This might be from an error detected on a bus
in the memory system.
Usage fault
A usage fault is an exception that occurs because of a fault related to instruction
execution. This includes:
– an undefined instruction
– an illegal unaligned access
– invalid state on instruction execution
– an error on exception return.
The following can cause a usage fault when the core is configured to report them:
– an unaligned address on word and halfword memory access
– division by zero.
SVCall
A supervisor call (SVC) is an exception that is triggered by the SVC instruction. In an
OS environment, applications can use SVC instructions to access OS kernel functions
and device drivers.
PendSV
PendSV is an interrupt-driven request for system-level service. In an OS environment,
use PendSV for context switching when no other exception is active.
SysTick
A SysTick exception is an exception the system timer generates when it reaches zero.
Software can also generate a SysTick exception. In an OS environment, the
processor can use this exception as system tick.
Interrupt (IRQ)
A interrupt, or IRQ, is an exception signalled by a peripheral, or generated by a
software request. All interrupts are asynchronous to instruction execution. In the
system, peripherals use interrupts to communicate with the processor.
Exception
type
Reset
NMI
Hard fault
Memory
management fault
All information provided in this document is subject to legal disclaimers.
Rev. 2 — 19 August 2010
Priority
-3, the highest
-2
-1
Configurable
[3]
Chapter 34: Appendix: Cortex-M3 user guide
Vector address
or offset
0x00000004
0x00000008
0x0000000C
0x00000010
[2]
Activation
Asynchronous
Asynchronous
-
Synchronous
UM10360
© NXP B.V. 2010. All rights reserved.
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