LPC1769FBD100,551 NXP Semiconductors, LPC1769FBD100,551 Datasheet - Page 88
![IC ARM CORTEX MCU 512K 100-LQFP](/photos/6/65/66516/568-100-lqfp_sot407-1_sml.jpg)
LPC1769FBD100,551
Manufacturer Part Number
LPC1769FBD100,551
Description
IC ARM CORTEX MCU 512K 100-LQFP
Manufacturer
NXP Semiconductors
Series
LPC17xxr
Datasheets
1.OM11043.pdf
(79 pages)
2.LPC1767FBD100551.pdf
(2 pages)
3.LPC1767FBD100551.pdf
(840 pages)
4.LPC1769FBD100551.pdf
(66 pages)
Specifications of LPC1769FBD100,551
Program Memory Type
FLASH
Program Memory Size
512KB (512K x 8)
Package / Case
100-LQFP
Core Processor
ARM® Cortex-M3™
Core Size
32-Bit
Speed
120MHz
Connectivity
CAN, Ethernet, I²C, IrDA, Microwire, SPI, SSI, UART/USART, USB OTG
Peripherals
Brown-out Detect/Reset, DMA, I²S, Motor Control PWM, POR, PWM, WDT
Number Of I /o
70
Ram Size
64K x 8
Voltage - Supply (vcc/vdd)
2.4 V ~ 3.6 V
Data Converters
A/D 8x12b, D/A 1x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Processor Series
LPC17
Core
ARM Cortex M3
Data Bus Width
32 bit
Data Ram Size
64 KB
Interface Type
Ethernet, USB, OTG, CAN
Maximum Clock Frequency
120 MHz
Number Of Programmable I/os
70
Number Of Timers
4
Operating Supply Voltage
3.3 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
MDK-ARM, RL-ARM, ULINK2, MCB1760, MCB1760U, MCB1760UME
Minimum Operating Temperature
- 40 C
On-chip Adc
12 bit, 8 Channel
On-chip Dac
10 bit
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
622-1005 - USB IN-CIRCUIT PROG ARM7 LPC2K
Eeprom Size
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Other names
568-4966
935290522551
935290522551
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
LPC1769FBD100,551
Manufacturer:
NXP Semiconductors
Quantity:
10 000
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NXP Semiconductors
Table 65.
Table 66.
Table 67.
UM10360
User manual
Bit
2:0
7:3
10:8
15:11 IP_SPI
18:16 Unimplemented
23:19 IP_SSP0
26:24 Unimplemented
31:27 IP_SSP1
Bit
2:0
7:3
10:8
15:11 IP_RTC
18:16 Unimplemented
23:19 IP_EINT0
26:24 Unimplemented
31:27 IP_EINT1
Bit
2:0
7:3
10:8
15:11 IP_EINT3
18:16 Unimplemented
23:19 IP_ADC
26:24 Unimplemented
31:27 IP_BOD
Name
Unimplemented
IP_I2C2
Unimplemented
Name
Unimplemented
IP_PLL0
Unimplemented
Name
Unimplemented
IP_EINT2
Unimplemented
Interrupt Priority Register 3 (IPR3 - 0xE000 E40C)
Interrupt Priority Register 4 (IPR4 - 0xE000 E410)
Interrupt Priority Register 5 (IPR5 - 0xE000 E414)
6.5.14 Interrupt Priority Register 3 (IPR3 - 0xE000 E40C)
6.5.15 Interrupt Priority Register 4 (IPR4 - 0xE000 E410)
6.5.16 Interrupt Priority Register 5 (IPR5 - 0xE000 E414)
The IPR3 register controls the priority of the fourth group of 4 peripheral interrupts. Each
interrupt can have one of 32 priorities, where 0 is the highest priority.
The IPR4 register controls the priority of the fifth group of 4 peripheral interrupts. Each
interrupt can have one of 32 priorities, where 0 is the highest priority.
The IPR5 register controls the priority of the sixth group of 4 peripheral interrupts. Each
interrupt can have one of 32 priorities, where 0 is the highest priority.
Function
These bits ignore writes, and read as 0.
I
These bits ignore writes, and read as 0.
SPI Interrupt Priority. See functional description for bits 7-3.
These bits ignore writes, and read as 0.
SSP0 Interrupt Priority. See functional description for bits 7-3.
These bits ignore writes, and read as 0.
SSP1 Interrupt Priority. See functional description for bits 7-3.
Function
These bits ignore writes, and read as 0.
PLL0 (Main PLL) Interrupt Priority. 0 = highest priority. 31 (0x1F) = lowest priority.
These bits ignore writes, and read as 0.
Real Time Clock (RTC) Interrupt Priority. See functional description for bits 7-3.
These bits ignore writes, and read as 0.
External Interrupt 0 Interrupt Priority. See functional description for bits 7-3.
These bits ignore writes, and read as 0.
External Interrupt 1 Interrupt Priority. See functional description for bits 7-3.
Function
These bits ignore writes, and read as 0.
External Interrupt 2 Interrupt Priority. 0 = highest priority. 31 (0x1F) = lowest priority.
These bits ignore writes, and read as 0.
External Interrupt 3 Interrupt Priority. See functional description for bits 7-3.
These bits ignore writes, and read as 0.
ADC Interrupt Priority. See functional description for bits 7-3.
These bits ignore writes, and read as 0.
BOD Interrupt Priority. See functional description for bits 7-3.
2
C2 Interrupt Priority. 0 = highest priority. 31 (0x1F) = lowest priority.
All information provided in this document is subject to legal disclaimers.
Chapter 6: LPC17xx Nested Vectored Interrupt Controller (NVIC)
Rev. 2 — 19 August 2010
UM10360
© NXP B.V. 2010. All rights reserved.
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