LPC1769FBD100,551 NXP Semiconductors, LPC1769FBD100,551 Datasheet - Page 355

• Manufacturer Part Number: LPC1769FBD100,551
• Description: IC ARM CORTEX MCU 512K 100-LQFP
• Manufacturer: NXP Semiconductors
• Series: LPC17xxr

Specifications of LPC1769FBD100,551

• Program Memory Type: FLASH
• Program Memory Size: 512KB (512K x 8)
• Package / Case: 100-LQFP
• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 120MHz
• Connectivity: CAN, Ethernet, I²C, IrDA, Microwire, SPI, SSI, UART/USART, USB OTG
• Peripherals: Brown-out Detect/Reset, DMA, I²S, Motor Control PWM, POR, PWM, WDT
• Number Of I /o: 70
• Ram Size: 64K x 8
• Voltage - Supply (vcc/vdd): 2.4 V ~ 3.6 V
• Data Converters: A/D 8x12b, D/A 1x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Processor Series: LPC17
• Core: ARM Cortex M3
• Data Bus Width: 32 bit
• Data Ram Size: 64 KB
• Interface Type: Ethernet, USB, OTG, CAN
• Maximum Clock Frequency: 120 MHz
• Number Of Programmable I/os: 70
• Number Of Timers: 4
• Operating Supply Voltage: 3.3 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2, MCB1760, MCB1760U, MCB1760UME
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 12 bit, 8 Channel
• On-chip Dac: 10 bit
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 622-1005 - USB IN-CIRCUIT PROG ARM7 LPC2K
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 568-4966; 935290522551

NXP Semiconductors
Table 319. CAN Global Status Register (CAN1GSR - address 0x4004 4008, CAN2GSR - address 0x4004 8008) bit
[1]
UM10360
User manual
Bit
0
1
2
3
4
5
6
7
15:8
23:16 RXERR -
31:24 TXERR -
After reading all messages and releasing their memory space with the command 'Release Receive Buffer,' this bit is cleared.
Symbol Value
RBS
DOS
TBS
TCS
RS
TS
ES
BS
-
[4]
[5]
[6]
[4]
description
[3]
[1]
[2]
0 (empty)
1 (full)
0 (absent)
1 (overrun)
0 (locked)
1 (released)
0 (incomplete) At least one requested transmission has not been successfully completed
1 (complete)
0 (idle)
1 (receive)
0 (idle)
1 (transmit)
0 (ok)
1 (error)
0 (Bus-On)
1 (Bus-Off)
-
Function
Receive Buffer Status.
No message is available.
At least one complete message is received by the Double Receive Buffer
and available in the CANxRFS, CANxRID, and if applicable the CANxRDA
and CANxRDB registers. This bit is cleared by the Release Receive Buffer
command in CANxCMR, if no subsequent received message is available.
Data Overrun Status.
No data overrun has occurred since the last Clear Data Overrun command
was given/written to CANxCMR (or since Reset).
A message was lost because the preceding message to this CAN controller
was not read and released quickly enough (there was not enough space for
a new message in the Double Receive Buffer).
Transmit Buffer Status.
At least one of the Transmit Buffers is not available for the CPU, i.e. at least
one previously queued message for this CAN controller has not yet been
sent, and therefore software should not write to the CANxTFI, CANxTID,
CANxTDA, nor CANxTDB registers of that (those) Tx buffer(s).
All three Transmit Buffers are available for the CPU. No transmit message is
pending for this CAN controller (in any of the 3 Tx buffers), and software may
write to any of the CANxTFI, CANxTID, CANxTDA, and CANxTDB registers.
Transmit Complete Status.
yet.
All requested transmission(s) has (have) been successfully completed.
Receive Status.
The CAN controller is idle.
The CAN controller is receiving a message.
Transmit Status.
The CAN controller is idle.
The CAN controller is sending a message.
Error Status.
Both error counters are below the Error Warning Limit.
One or both of the Transmit and Receive Error Counters has reached the
limit set in the Error Warning Limit register.
Bus Status.
The CAN Controller is involved in bus activities
The CAN controller is currently not involved/prohibited from bus activity
because the Transmit Error Counter reached its limiting value of 255.
Reserved, user software should not write ones to reserved bits. The value
read from a reserved bit is not defined.
The current value of the Rx Error Counter (an 8-bit value).
The current value of the Tx Error Counter (an 8-bit value).
All information provided in this document is subject to legal disclaimers.
Rev. 2 — 19 August 2010
Chapter 16: LPC17xx CAN1/2
UM10360
© NXP B.V. 2010. All rights reserved.
Reset
Value
0
0
1
1
1
1
0
0
NA
0
0
355 of 840
0
0
X
X
RM
Set
1
x
0
0
0
0