LPC1769FBD100,551 NXP Semiconductors, LPC1769FBD100,551 Datasheet - Page 141

• Manufacturer Part Number: LPC1769FBD100,551
• Description: IC ARM CORTEX MCU 512K 100-LQFP
• Manufacturer: NXP Semiconductors
• Series: LPC17xxr

Specifications of LPC1769FBD100,551

• Program Memory Type: FLASH
• Program Memory Size: 512KB (512K x 8)
• Package / Case: 100-LQFP
• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 120MHz
• Connectivity: CAN, Ethernet, I²C, IrDA, Microwire, SPI, SSI, UART/USART, USB OTG
• Peripherals: Brown-out Detect/Reset, DMA, I²S, Motor Control PWM, POR, PWM, WDT
• Number Of I /o: 70
• Ram Size: 64K x 8
• Voltage - Supply (vcc/vdd): 2.4 V ~ 3.6 V
• Data Converters: A/D 8x12b, D/A 1x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Processor Series: LPC17
• Core: ARM Cortex M3
• Data Bus Width: 32 bit
• Data Ram Size: 64 KB
• Interface Type: Ethernet, USB, OTG, CAN
• Maximum Clock Frequency: 120 MHz
• Number Of Programmable I/os: 70
• Number Of Timers: 4
• Operating Supply Voltage: 3.3 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2, MCB1760, MCB1760U, MCB1760UME
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 12 bit, 8 Channel
• On-chip Dac: 10 bit
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 622-1005 - USB IN-CIRCUIT PROG ARM7 LPC2K
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 568-4966; 935290522551

10.1 Basic configuration
10.2 Introduction
UM10360
User manual
The Ethernet controller is configured using the following registers:
The Ethernet block contains a full featured 10 Mbps or 100 Mbps Ethernet MAC (Media
Access Controller) designed to provide optimized performance through the use of DMA
hardware acceleration. Features include a generous suite of control registers, half or full
duplex operation, flow control, control frames, hardware acceleration for transmit retry,
receive packet filtering and wake-up on LAN activity. Automatic frame transmission and
reception with Scatter-Gather DMA off-loads many operations from the CPU.
The Ethernet block is an AHB master that drives the AHB bus matrix. Through the matrix,
it has access to all on-chip RAM memories. A recommended use of RAM by the Ethernet
is to use one of the RAM blocks exclusively for Ethernet traffic. That RAM would then be
accessed only by the Ethernet and the CPU, and possibly the GPDMA, giving maximum
bandwidth to the Ethernet function.
The Ethernet block interfaces between an off-chip Ethernet PHY using the RMII (Reduced
Media Independent Interface) protocol and the on-chip MIIM (Media Independent
Interface Management) serial bus, also referred to as MDIO (Management Data
Input/Output).
Table 124. Ethernet acronyms, abbreviations, and definitions
Acronym or
Abbreviation
AHB
CRC
DMA
Double-word
FCS
Fragment
1. Power: In the PCONP register
2. Clock: see
3. Pins: Enable Ethernet pins through the PINSEL registers and select their modes
4. Wake-up: Activity on the Ethernet port can wake up the microcontroller from
5. Interrupts: Interrupts are enabled in the NVIC using the appropriate Interrupt Set
6. Initialization: see
UM10360
Chapter 10: LPC17xx Ethernet
Rev. 2 — 19 August 2010
Remark: On reset, the Ethernet block is disabled (PCENET = 0).
through the PINMODE registers, see
Power-down mode, see
Enable register.
Table
All information provided in this document is subject to legal disclaimers.
Definition
Advanced High-performance bus
Cyclic Redundancy Check
Direct Memory Access
64-bit entity
Frame Check Sequence (CRC)
A (part of an) Ethernet frame; one or multiple fragments can add up to a single
Ethernet frame.
38.
Section
Rev. 2 — 19 August 2010
Section
10.17.2.
(Table
4.8.8.
46), set bit PCENET.
Section
8.5.
© NXP B.V. 2010. All rights reserved.
User manual
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