LPC1769FBD100,551 NXP Semiconductors, LPC1769FBD100,551 Datasheet - Page 64

• Manufacturer Part Number: LPC1769FBD100,551
• Description: IC ARM CORTEX MCU 512K 100-LQFP
• Manufacturer: NXP Semiconductors
• Series: LPC17xxr

Specifications of LPC1769FBD100,551

• Program Memory Type: FLASH
• Program Memory Size: 512KB (512K x 8)
• Package / Case: 100-LQFP
• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 120MHz
• Connectivity: CAN, Ethernet, I²C, IrDA, Microwire, SPI, SSI, UART/USART, USB OTG
• Peripherals: Brown-out Detect/Reset, DMA, I²S, Motor Control PWM, POR, PWM, WDT
• Number Of I /o: 70
• Ram Size: 64K x 8
• Voltage - Supply (vcc/vdd): 2.4 V ~ 3.6 V
• Data Converters: A/D 8x12b, D/A 1x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Processor Series: LPC17
• Core: ARM Cortex M3
• Data Bus Width: 32 bit
• Data Ram Size: 64 KB
• Interface Type: Ethernet, USB, OTG, CAN
• Maximum Clock Frequency: 120 MHz
• Number Of Programmable I/os: 70
• Number Of Timers: 4
• Operating Supply Voltage: 3.3 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2, MCB1760, MCB1760U, MCB1760UME
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 12 bit, 8 Channel
• On-chip Dac: 10 bit
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 622-1005 - USB IN-CIRCUIT PROG ARM7 LPC2K
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 568-4966; 935290522551

NXP Semiconductors
UM10360
User manual
4.8.10 Power control usage notes
4.8.11 Power domains
Table 46.
Note that the DAC peripheral does not have a control bit in PCONP. To enable the DAC,
its output must be selected to appear on the related pin, P0.26, by configuring the
PINSEL1 register. See
0x4002
After every reset, the PCONP register contains the value that enables selected interfaces
and peripherals controlled by the PCONP to be enabled. Therefore, apart from proper
configuring via peripheral dedicated registers, the user’s application might have to access
the PCONP in order to start using some of the on-board peripherals.
Power saving oriented systems should have 1s in the PCONP register only in positions
that match peripherals really used in the application. All other bits, declared to be
"Reserved" or dedicated to the peripherals not used in the current application, must be
cleared to 0.
The LPC17xx provides two independent power domains that allow the bulk of the device
to have power removed while maintaining operation of the Real Time Clock.
The VBAT pin supplies power only to the RTC domain. The RTC requires a minimum of
power to operate, which can be supplied by an external battery. Whenever the device core
power is present, that power is used to operate the RTC, causing no power drain from a
battery when main power is available.
Bit
27
28
29
30
31
Symbol
PCI2S
-
PCGPDMA
PCENET
PCUSB
C004)”.
Power Control for Peripherals register (PCONP - address 0x400F C0C4) bit
description
All information provided in this document is subject to legal disclaimers.
Description
I
Reserved.
GPDMA function power/clock control bit.
Ethernet block power/clock control bit.
USB interface power/clock control bit.
2
S interface power/clock control bit.
Rev. 2 — 19 August 2010
Section 8.5.2 “Pin Function Select Register 1 (PINSEL1 -
Chapter 4: LPC17xx Clocking and power control
UM10360
© NXP B.V. 2010. All rights reserved.
64 of 840
Reset
value
0
NA
0
0
0