LPC1769FBD100,551 NXP Semiconductors, LPC1769FBD100,551 Datasheet - Page 698

• Manufacturer Part Number: LPC1769FBD100,551
• Description: IC ARM CORTEX MCU 512K 100-LQFP
• Manufacturer: NXP Semiconductors
• Series: LPC17xxr

Specifications of LPC1769FBD100,551

• Program Memory Type: FLASH
• Program Memory Size: 512KB (512K x 8)
• Package / Case: 100-LQFP
• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 120MHz
• Connectivity: CAN, Ethernet, I²C, IrDA, Microwire, SPI, SSI, UART/USART, USB OTG
• Peripherals: Brown-out Detect/Reset, DMA, I²S, Motor Control PWM, POR, PWM, WDT
• Number Of I /o: 70
• Ram Size: 64K x 8
• Voltage - Supply (vcc/vdd): 2.4 V ~ 3.6 V
• Data Converters: A/D 8x12b, D/A 1x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Processor Series: LPC17
• Core: ARM Cortex M3
• Data Bus Width: 32 bit
• Data Ram Size: 64 KB
• Interface Type: Ethernet, USB, OTG, CAN
• Maximum Clock Frequency: 120 MHz
• Number Of Programmable I/os: 70
• Number Of Timers: 4
• Operating Supply Voltage: 3.3 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2, MCB1760, MCB1760U, MCB1760UME
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 12 bit, 8 Channel
• On-chip Dac: 10 bit
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 622-1005 - USB IN-CIRCUIT PROG ARM7 LPC2K
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 568-4966; 935290522551

NXP Semiconductors
UM10360
User manual
34.2.7.1.1 Syntax
34.2.7.1.2 Operation
34.2.7.1 SSAT and USAT
34.2.7 Saturating instructions
This section describes the saturating instructions, SSAT and USAT.
Signed Saturate and Unsigned Saturate to any bit position, with optional shift before
saturating.
op{cond} Rd, #n, Rm {, shift #s}
where:
op is one of:
cond is an optional condition code, see
Rd is the destination register.
n specifies the bit position to saturate to:
Rm is the register containing the value to saturate.
shift #s is an optional shift applied to Rm before saturating. It must be one of the following:
These instructions saturate to a signed or unsigned n-bit value.
The SSAT instruction applies the specified shift, then saturates to the signed range
−2
The USAT instruction applies the specified shift, then saturates to the unsigned range
0 ≤ x ≤ 2
For signed n-bit saturation using SSAT, this means that:
For unsigned n-bit saturation using USAT, this means that:
•
•
•
•
•
•
•
SSAT Saturates a signed value to a signed range.
USAT Saturates a signed value to an unsigned range.
ASR #s: where s is in the range 1 to 31
LSL #s: where s is in the range 0 to 31.
n–1
n ranges from 1 to 32 for SSAT.
n ranges from 0 to 31 for USAT.
if the value to be saturated is less than −2
if the value to be saturated is greater than 2
otherwise, the result returned is the same as the value to be saturated.
if the value to be saturated is less than 0, the result returned is 0
if the value to be saturated is greater than 2
≤ x ≤ 2
n
−1.
n–1
−1.
All information provided in this document is subject to legal disclaimers.
Rev. 2 — 19 August 2010
Section 34.2.3.7 “Conditional
Chapter 34: Appendix: Cortex-M3 user guide
n-1
n-1
n
, the result returned is −2
−1, the result returned is 2
−1, the result returned is 2
execution”.
UM10360
© NXP B.V. 2010. All rights reserved.
n-1
n
−1
n-1
−1
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