LPC1769FBD100,551 NXP Semiconductors, LPC1769FBD100,551 Datasheet - Page 71
LPC1769FBD100,551
Manufacturer Part Number
LPC1769FBD100,551
Description
IC ARM CORTEX MCU 512K 100-LQFP
Manufacturer
NXP Semiconductors
Series
LPC17xxr
Datasheets
1.OM11043.pdf
(79 pages)
2.LPC1767FBD100551.pdf
(2 pages)
3.LPC1767FBD100551.pdf
(840 pages)
4.LPC1769FBD100551.pdf
(66 pages)
Specifications of LPC1769FBD100,551
Program Memory Type
FLASH
Program Memory Size
512KB (512K x 8)
Package / Case
100-LQFP
Core Processor
ARM® Cortex-M3™
Core Size
32-Bit
Speed
120MHz
Connectivity
CAN, Ethernet, I²C, IrDA, Microwire, SPI, SSI, UART/USART, USB OTG
Peripherals
Brown-out Detect/Reset, DMA, I²S, Motor Control PWM, POR, PWM, WDT
Number Of I /o
70
Ram Size
64K x 8
Voltage - Supply (vcc/vdd)
2.4 V ~ 3.6 V
Data Converters
A/D 8x12b, D/A 1x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Processor Series
LPC17
Core
ARM Cortex M3
Data Bus Width
32 bit
Data Ram Size
64 KB
Interface Type
Ethernet, USB, OTG, CAN
Maximum Clock Frequency
120 MHz
Number Of Programmable I/os
70
Number Of Timers
4
Operating Supply Voltage
3.3 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
MDK-ARM, RL-ARM, ULINK2, MCB1760, MCB1760U, MCB1760UME
Minimum Operating Temperature
- 40 C
On-chip Adc
12 bit, 8 Channel
On-chip Dac
10 bit
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
622-1005 - USB IN-CIRCUIT PROG ARM7 LPC2K
Eeprom Size
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Other names
568-4966
935290522551
935290522551
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
LPC1769FBD100,551
Manufacturer:
NXP Semiconductors
Quantity:
10 000
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NXP Semiconductors
UM10360
User manual
If a flash instruction fetch and a flash data access from the CPU occur at the same time,
the multilayer matrix gives precedence to the data access. This is because a stalled data
access always slows down execution, while a stalled instruction fetch often does not.
When the flash data access is concluded, any flash fetch or prefetch that had been in
progress is re-initiated.
Branches and other program flow changes cause a break in the sequential flow of
instruction fetches described above. Buffer replacement strategy in the flash accelerator
attempts to maximize the chances that potentially reusable information is retained until it
is needed again.
If an attempt is made to write directly to the flash memory without using the normal flash
programming interface (via Boot ROM function calls), the flash accelerator generates an
error condition. The CPU treats this error as a data abort. The GPDMA handles error
conditions as described in
When an Instruction Fetch is not satisfied by existing contents of the buffer array, nor has
a prefetch been initiated for that flash line, the CPU will be stalled while a fetch is initiated
for the related 128-bit flash line. If a prefetch has been initiated but not yet completed, the
CPU is stalled for a shorter time since the required flash access is already in progress.
Typically, a flash prefetch is begun whenever an access is made to a just prefetched
address, or to a buffer whose immediate successor is not already in another buffer. A
prefetch in progress may be aborted by a data access, in order to minimize CPU stalls.
A prefetched flash line is latched within the flash memory, but the flash accelerator does
not capture the line in a buffer until the CPU presents an address that is contained within
the prefetched flash line. If the core presents an instruction address that is not already
buffered and is not contained in the prefetched flash line, the prefetched line will be
discarded.
Some special cases include the possibility that the CPU will request a data access to an
address already contained in an instruction buffer. In this case, the data will be read from
the buffer as if it was a data buffer. The reverse case, if the CPU requests an instruction
address that can be satisfied from an existing data buffer, causes the instruction to be
supplied from the data buffer, and the buffer to be changed into an instruction buffer. This
causes the buffer to be handled differently when the flash accelerator is determining which
buffer is to be overwritten next.
All information provided in this document is subject to legal disclaimers.
Rev. 2 — 19 August 2010
Section
31.4.1.6.3.
Chapter 5: LPC17xx Flash accelerator
UM10360
© NXP B.V. 2010. All rights reserved.
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