LPC1769FBD100,551 NXP Semiconductors, LPC1769FBD100,551 Datasheet - Page 187
![IC ARM CORTEX MCU 512K 100-LQFP](/photos/6/65/66516/568-100-lqfp_sot407-1_sml.jpg)
LPC1769FBD100,551
Manufacturer Part Number
LPC1769FBD100,551
Description
IC ARM CORTEX MCU 512K 100-LQFP
Manufacturer
NXP Semiconductors
Series
LPC17xxr
Datasheets
1.OM11043.pdf
(79 pages)
2.LPC1767FBD100551.pdf
(2 pages)
3.LPC1767FBD100551.pdf
(840 pages)
4.LPC1769FBD100551.pdf
(66 pages)
Specifications of LPC1769FBD100,551
Program Memory Type
FLASH
Program Memory Size
512KB (512K x 8)
Package / Case
100-LQFP
Core Processor
ARM® Cortex-M3™
Core Size
32-Bit
Speed
120MHz
Connectivity
CAN, Ethernet, I²C, IrDA, Microwire, SPI, SSI, UART/USART, USB OTG
Peripherals
Brown-out Detect/Reset, DMA, I²S, Motor Control PWM, POR, PWM, WDT
Number Of I /o
70
Ram Size
64K x 8
Voltage - Supply (vcc/vdd)
2.4 V ~ 3.6 V
Data Converters
A/D 8x12b, D/A 1x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Processor Series
LPC17
Core
ARM Cortex M3
Data Bus Width
32 bit
Data Ram Size
64 KB
Interface Type
Ethernet, USB, OTG, CAN
Maximum Clock Frequency
120 MHz
Number Of Programmable I/os
70
Number Of Timers
4
Operating Supply Voltage
3.3 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
MDK-ARM, RL-ARM, ULINK2, MCB1760, MCB1760U, MCB1760UME
Minimum Operating Temperature
- 40 C
On-chip Adc
12 bit, 8 Channel
On-chip Dac
10 bit
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
622-1005 - USB IN-CIRCUIT PROG ARM7 LPC2K
Eeprom Size
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Other names
568-4966
935290522551
935290522551
Available stocks
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Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
LPC1769FBD100,551
Manufacturer:
NXP Semiconductors
Quantity:
10 000
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NXP Semiconductors
UM10360
User manual
boundary. Since the number of descriptors matches the number of statuses the status
array consists of four elements; the array is 4x1x4 bytes and aligned on a 4 byte address
boundary. The device driver writes the base address of the descriptor array
(0x2008 10EC) to the TxDescriptor register and the base address of the status array
(0x2008 11F8) to the TxStatus register. The device driver writes the number of descriptors
and statuses minus 1(3) to the TxDescriptorNumber register. The descriptors and
statuses in the arrays need not be initialized, yet.
At this point, the transmit data path may be enabled by setting the TxEnable bit in the
Command register. If the transmit data path is enabled while there are no further frames to
send the TxFinishedInt interrupt flag will be set. To reduce the processor interrupt load
only the desired interrupts can be enabled by setting the relevant bits in the IntEnable
register.
Now suppose application software wants to transmit a frame of 12 bytes using a TCP/IP
protocol (in real applications frames will be larger than 12 bytes). The TCP/IP stack will
add a header to the frame. The frame header need not be immediately in front of the
payload data in memory. The device driver can program the Tx DMA to collect header and
payload data. To do so, the device driver will program the first descriptor to point at the
frame header; the Last flag in the descriptor will be set to false/0 to indicate a
multi-fragment transmission. The device driver will program the next descriptor to point at
the actual payload data. The maximum size of a payload buffer is 2 kB so a single
descriptor suffices to describe the payload buffer. For the sake of the example though the
payload is distributed across two descriptors. After the first descriptor in the array
describing the header, the second descriptor in the array describes the initial 8 bytes of
the payload; the third descriptor in the array describes the remaining 4 bytes of the frame.
In the third descriptor the Last bit in the Control word is set to true/1 to indicate it is the last
descriptor in the frame. In this example the Interrupt bit in the descriptor Control field is set
in the last fragment of the frame in order to trigger an interrupt after the transmission
completed. The Size field in the descriptor’s Control word is set to the number of bytes in
the fragment buffer, -1 encoded.
Note that in real device drivers, the payload will typically only be split across multiple
descriptors if it is more than 2 kB. Also note that transmission payload data is forwarded to
the hardware without the device driver copying it (zero copy device driver).
After setting up the descriptors for the transaction the device driver increments the
TxProduceIndex register by 3 since three descriptors have been programmed. If the
transmit data path was not enabled during initialization the device driver needs to enable
the data path now.
If the transmit data path is enabled the Ethernet block will start transmitting the frame as
soon as it detects the TxProduceIndex is not equal to TxConsumeIndex - both were zero
after reset. The Tx DMA will start reading the descriptors from memory. The memory
system will return the descriptors and the Ethernet block will accept them one by one
while reading the transmit data fragments.
As soon as transmission read data is returned from memory, the Ethernet block will try to
start transmission on the Ethernet connection via the RMII interface.
All information provided in this document is subject to legal disclaimers.
Rev. 2 — 19 August 2010
Chapter 10: LPC17xx Ethernet
UM10360
© NXP B.V. 2010. All rights reserved.
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