LPC1769FBD100,551 NXP Semiconductors, LPC1769FBD100,551 Datasheet - Page 728

• Manufacturer Part Number: LPC1769FBD100,551
• Description: IC ARM CORTEX MCU 512K 100-LQFP
• Manufacturer: NXP Semiconductors
• Series: LPC17xxr

Specifications of LPC1769FBD100,551

• Program Memory Type: FLASH
• Program Memory Size: 512KB (512K x 8)
• Package / Case: 100-LQFP
• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 120MHz
• Connectivity: CAN, Ethernet, I²C, IrDA, Microwire, SPI, SSI, UART/USART, USB OTG
• Peripherals: Brown-out Detect/Reset, DMA, I²S, Motor Control PWM, POR, PWM, WDT
• Number Of I /o: 70
• Ram Size: 64K x 8
• Voltage - Supply (vcc/vdd): 2.4 V ~ 3.6 V
• Data Converters: A/D 8x12b, D/A 1x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Processor Series: LPC17
• Core: ARM Cortex M3
• Data Bus Width: 32 bit
• Data Ram Size: 64 KB
• Interface Type: Ethernet, USB, OTG, CAN
• Maximum Clock Frequency: 120 MHz
• Number Of Programmable I/os: 70
• Number Of Timers: 4
• Operating Supply Voltage: 3.3 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2, MCB1760, MCB1760U, MCB1760UME
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 12 bit, 8 Channel
• On-chip Dac: 10 bit
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 622-1005 - USB IN-CIRCUIT PROG ARM7 LPC2K
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 568-4966; 935290522551

NXP Semiconductors
Table 626.
UM10360
User manual
Name
R0-R12
MSP
PSP
LR
PC
PSR
ASPR
IPSR
Core register set summary
34.3.1.3 Core registers
Type
RW
RW
RW
RW
RW
RW
RW
RO
Table 625. Summary of processor mode, execution privilege level, and stack use options
[1]
The processor core registers are:
Processor
mode
Thread
Handler
[1]
See
Program Counter
High registers
Low registers
Stack Pointer
Table
Link Register
634.
Required
privilege
Either
Privileged
Either
Either
Either
Privileged
Either
Privileged
All information provided in this document is subject to legal disclaimers.
[2]
Rev. 2 — 19 August 2010
Used to
execute
Applications
Exception handlers
FAULTMASK
CONTROL
PRIMASK
BASEPRI
PC (R15)
SP (R13)
LR (R14)
PSR
R10
R11
R12
R0
R1
R2
R3
R4
R5
R6
R7
R8
R9
Reset
value
Undefined
See description
Undefined
0xFFFFFFFF
See description
0x01000000
0x00000000
0x00000000
General-purpose registers
Program status register
Exception mask registers
CONTROL register
Chapter 34: Appendix: Cortex-M3 user guide
PSP
Privileged or
Privilege level for
software execution
unprivileged
Always privileged
‡
Description
Section 34.3.1.3.1
Section 34.3.1.3.2
Section 34.3.1.3.2
Section 34.3.1.3.3
Section 34.3.1.3.4
Section 34.3.1.3.5
Table 628
Table 629
[1]
MSP
‡
Stack used
Main stack or process
stack
Main stack
Special registers
‡
Banked version of SP
UM10360
© NXP B.V. 2010. All rights reserved.
[1]
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