LPC1769FBD100,551 NXP Semiconductors, LPC1769FBD100,551 Datasheet - Page 148

• Manufacturer Part Number: LPC1769FBD100,551
• Description: IC ARM CORTEX MCU 512K 100-LQFP
• Manufacturer: NXP Semiconductors
• Series: LPC17xxr

Specifications of LPC1769FBD100,551

• Program Memory Type: FLASH
• Program Memory Size: 512KB (512K x 8)
• Package / Case: 100-LQFP
• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 120MHz
• Connectivity: CAN, Ethernet, I²C, IrDA, Microwire, SPI, SSI, UART/USART, USB OTG
• Peripherals: Brown-out Detect/Reset, DMA, I²S, Motor Control PWM, POR, PWM, WDT
• Number Of I /o: 70
• Ram Size: 64K x 8
• Voltage - Supply (vcc/vdd): 2.4 V ~ 3.6 V
• Data Converters: A/D 8x12b, D/A 1x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Processor Series: LPC17
• Core: ARM Cortex M3
• Data Bus Width: 32 bit
• Data Ram Size: 64 KB
• Interface Type: Ethernet, USB, OTG, CAN
• Maximum Clock Frequency: 120 MHz
• Number Of Programmable I/os: 70
• Number Of Timers: 4
• Operating Supply Voltage: 3.3 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2, MCB1760, MCB1760U, MCB1760UME
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 12 bit, 8 Channel
• On-chip Dac: 10 bit
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 622-1005 - USB IN-CIRCUIT PROG ARM7 LPC2K
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 568-4966; 935290522551

NXP Semiconductors
10.10 Registers and software interface
Table 128. Ethernet register definitions
UM10360
User manual
Name
MAC registers
MAC1
MAC2
IPGT
IPGR
CLRT
MAXF
SUPP
TEST
MCFG
MCMD
MADR
MWTD
MRDD
MIND
SA0
SA1
SA2
Control registers
Command
10.10.1 Register map
The software interface of the Ethernet block consists of a register view and the format
definitions for the transmit and receive descriptors. These two aspects are addressed in
the next two subsections.
Table 128
AHB address space required is 4 kilobytes.
After a hard reset or a soft reset via the RegReset bit of the Command register all bits in
all registers are reset to 0 unless stated otherwise in the following register descriptions.
Some registers will have unused bits which will return a 0 on a read via the AHB interface.
Writing to unused register bits of an otherwise writable register will not have side effects.
The register map consists of registers in the Ethernet MAC and registers around the core
for controlling DMA transfers, flow control and filtering.
Reading from reserved addresses or reserved bits leads to unpredictable data. Writing to
reserved addresses or reserved bits has no effect.
Reading of write-only registers will return a read error on the AHB interface. Writing of
read-only registers will return a write error on the AHB interface.
Description
MAC configuration register 1.
MAC configuration register 2.
Back-to-Back Inter-Packet-Gap register.
Non Back-to-Back Inter-Packet-Gap register.
Collision window / Retry register.
Maximum Frame register.
PHY Support register.
Test register.
MII Mgmt Configuration register.
MII Mgmt Command register.
MII Mgmt Address register.
MII Mgmt Write Data register.
MII Mgmt Read Data register.
MII Mgmt Indicators register.
Station Address 0 register.
Station Address 1 register.
Station Address 2 register.
Command register.
lists the registers, register addresses and other basic information. The total
All information provided in this document is subject to legal disclaimers.
Rev. 2 — 19 August 2010
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
RO
RO
R/W
R/W
Access
R/W
WO
R/W
R/W
Chapter 10: LPC17xx Ethernet
Reset Value
0x8000
0
0
0
0x370F
0x0600
0
0
0
0
0
0
0
0
0
0
0
0
UM10360
© NXP B.V. 2010. All rights reserved.
0x5000 000C
Address
0x5000 0000
0x5000 0004
0x5000 0008
0x5000 0010
0x5000 0014
0x5000 0018
0x5000 001C
0x5000 0020
0x5000 0024
0x5000 0028
0x5000 002C
0x5000 0030
0x5000 0034
0x5000 0040
0x5000 0044
0x5000 0048
0x5000 0100
148 of 840