LPC1769FBD100,551 NXP Semiconductors, LPC1769FBD100,551 Datasheet - Page 284
![IC ARM CORTEX MCU 512K 100-LQFP](/photos/6/65/66516/568-100-lqfp_sot407-1_sml.jpg)
LPC1769FBD100,551
Manufacturer Part Number
LPC1769FBD100,551
Description
IC ARM CORTEX MCU 512K 100-LQFP
Manufacturer
NXP Semiconductors
Series
LPC17xxr
Datasheets
1.OM11043.pdf
(79 pages)
2.LPC1767FBD100551.pdf
(2 pages)
3.LPC1767FBD100551.pdf
(840 pages)
4.LPC1769FBD100551.pdf
(66 pages)
Specifications of LPC1769FBD100,551
Program Memory Type
FLASH
Program Memory Size
512KB (512K x 8)
Package / Case
100-LQFP
Core Processor
ARM® Cortex-M3™
Core Size
32-Bit
Speed
120MHz
Connectivity
CAN, Ethernet, I²C, IrDA, Microwire, SPI, SSI, UART/USART, USB OTG
Peripherals
Brown-out Detect/Reset, DMA, I²S, Motor Control PWM, POR, PWM, WDT
Number Of I /o
70
Ram Size
64K x 8
Voltage - Supply (vcc/vdd)
2.4 V ~ 3.6 V
Data Converters
A/D 8x12b, D/A 1x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Processor Series
LPC17
Core
ARM Cortex M3
Data Bus Width
32 bit
Data Ram Size
64 KB
Interface Type
Ethernet, USB, OTG, CAN
Maximum Clock Frequency
120 MHz
Number Of Programmable I/os
70
Number Of Timers
4
Operating Supply Voltage
3.3 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
MDK-ARM, RL-ARM, ULINK2, MCB1760, MCB1760U, MCB1760UME
Minimum Operating Temperature
- 40 C
On-chip Adc
12 bit, 8 Channel
On-chip Dac
10 bit
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
622-1005 - USB IN-CIRCUIT PROG ARM7 LPC2K
Eeprom Size
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Other names
568-4966
935290522551
935290522551
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
LPC1769FBD100,551
Manufacturer:
NXP Semiconductors
Quantity:
10 000
- OM11043 PDF datasheet
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NXP Semiconductors
Table 266. I
UM10360
User manual
Bit
0
1
2
3
4
5
Symbol
TDIE
AFIE
NAIE
DRMIE
DRSIE
REFIE
13.8.13 I
2
C Control register (I2C_CTL - address 0x5000 C308) bit description
Value Description
0
1
0
1
0
1
0
1
0
1
0
1
Table 265. I
The I2C_CTL register is used to enable interrupts and reset the I
Enabled interrupts cause the USB_I2C_INT interrupt output line to be asserted when set.
Transmit Done Interrupt Enable. This enables the TDI interrupt signalling that this I
issued a STOP condition.
Disable the TDI interrupt.
Enable the TDI interrupt.
Transmitter Arbitration Failure Interrupt Enable. This enables the AFI interrupt which is
asserted during transmission when trying to set SDA high, but the bus is driven low by
another device.
Disable the AFI.
Enable the AFI.
Transmitter No Acknowledge Interrupt Enable. This enables the NAI interrupt signalling
that transmitted byte was not acknowledged.
Disable the NAI.
Enable the NAI.
Master Transmitter Data Request Interrupt Enable. This enables the DRMI interrupt which
signals that the master transmitter has run out of data, has not issued a STOP, and is
holding the SCL line low.
Disable the DRMI interrupt.
Enable the DRMI interrupt.
Slave Transmitter Data Request Interrupt Enable. This enables the DRSI interrupt which
signals that the slave transmitter has run out of data and the last byte was acknowledged,
so the SCL line is being held low.
Disable the DRSI interrupt.
Enable the DRSI interrupt.
Receive FIFO Full Interrupt Enable. This enables the Receive FIFO Full interrupt to
indicate that the receive FIFO cannot accept any more data.
Disable the RFFI.
Enable the RFFI.
Bit
11
31:12 -
2
C Control Register (I2C_CTL - 0x5000 C308)
Symbol Value Description
TFE
2
C status register (I2C_STS - address 0x5000 C304) bit description
All information provided in this document is subject to legal disclaimers.
0
1
NA
Rev. 2 — 19 August 2010
Transmit FIFO Empty. TFE is set when the TX FIFO is empty
and is cleared when the TX FIFO contains valid data.
TX FIFO contains valid data.
TX FIFO is empty
Reserved, user software should not write ones to reserved bits.
The value read from a reserved bit is not defined.
Chapter 13: LPC17xx USB OTG
2
C state machine.
UM10360
© NXP B.V. 2010. All rights reserved.
2
C
284 of 840
Reset
Value
1
NA
Reset
Value
0
0
0
0
0
0
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