LPC1769FBD100,551 NXP Semiconductors, LPC1769FBD100,551 Datasheet - Page 254

• Manufacturer Part Number: LPC1769FBD100,551
• Description: IC ARM CORTEX MCU 512K 100-LQFP
• Manufacturer: NXP Semiconductors
• Series: LPC17xxr

Specifications of LPC1769FBD100,551

• Program Memory Type: FLASH
• Program Memory Size: 512KB (512K x 8)
• Package / Case: 100-LQFP
• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 120MHz
• Connectivity: CAN, Ethernet, I²C, IrDA, Microwire, SPI, SSI, UART/USART, USB OTG
• Peripherals: Brown-out Detect/Reset, DMA, I²S, Motor Control PWM, POR, PWM, WDT
• Number Of I /o: 70
• Ram Size: 64K x 8
• Voltage - Supply (vcc/vdd): 2.4 V ~ 3.6 V
• Data Converters: A/D 8x12b, D/A 1x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Processor Series: LPC17
• Core: ARM Cortex M3
• Data Bus Width: 32 bit
• Data Ram Size: 64 KB
• Interface Type: Ethernet, USB, OTG, CAN
• Maximum Clock Frequency: 120 MHz
• Number Of Programmable I/os: 70
• Number Of Timers: 4
• Operating Supply Voltage: 3.3 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2, MCB1760, MCB1760U, MCB1760UME
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 12 bit, 8 Channel
• On-chip Dac: 10 bit
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 622-1005 - USB IN-CIRCUIT PROG ARM7 LPC2K
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 568-4966; 935290522551

NXP Semiconductors
11.15 DMA operation
UM10360
User manual
11.14.2 Data transfer for OUT endpoints
11.14.3 Data transfer for IN endpoints
All non-isochronous OUT endpoints generate an endpoint interrupt when they receive a
packet without an error. All non-isochronous IN endpoints generate an interrupt when a
packet is successfully transmitted, or when a NAK handshake is sent on the bus and the
interrupt on NAK feature is enabled.
For Isochronous endpoints, transfer of data is done when the FRAME interrupt (in
USBDevIntSt) occurs.
When the software wants to read the data from an endpoint buffer it should set the
RD_EN bit and program LOG_ENDPOINT with the desired endpoint number in the
USBCtrl register. The control logic will fetch the packet length to the USBRxPLen register,
and set the PKT_RDY bit
Software can now start reading the data from the USBRxData register
the end of packet is reached, the RD_EN bit is cleared, and the RxENDPKT bit is set in
the USBDevSt register. Software now issues a Clear Buffer (refer to
The endpoint is now ready to accept the next packet. For OUT isochronous endpoints, the
next packet will be received irrespective of whether the buffer has been cleared. Any data
not read from the buffer before the end of the frame is lost. See
buffered endpoint operation”
If the software clears RD_EN before the entire packet is read, reading is terminated, and
the data remains in the endpoint’s buffer. When RD_EN is set again for this endpoint, the
data will be read from the beginning.
When writing data to an endpoint buffer, WR_EN
(USBCtrl - 0x5000
send in the packet to the USBTxPLen register
continuously in the USBTxData register.
When the number of bytes programmed in USBTxPLen have been written to USBTxData,
the WR_EN bit is cleared, and the TxENDPKT bit is set in the USBDevIntSt register.
Software issues a Validate Buffer
Data:
isochronous endpoints, the data in the buffer will be sent only if the buffer is validated
before the next FRAME interrupt occurs; otherwise, an empty packet will be sent in the
next frame. If the software clears WR_EN before the entire packet is written, writing will
start again from the beginning the next time WR_EN is set for this endpoint.
Both RD_EN and WR_EN can be high at the same time for the same logical endpoint.
Interleaved read and write operation is possible.
In DMA mode, the DMA transfers data between RAM and the endpoint buffer.
The following sections discuss DMA mode operation. Background information is given in
sections
“Triggering the DMA
none)”) command. The endpoint is now ready to send the packet. For IN
Section 11.15.2 “USB device communication area”
All information provided in this document is subject to legal disclaimers.
C228)”) is set and software writes to the number of bytes it is going to
engine”. The fields of the DMA Descriptor are described in
Rev. 2 — 19 August 2010
(Table
for more details.
216).
(Section 11.12.14 “Validate Buffer (Command: 0xFA,
Chapter 11: LPC17xx USB device controller
(Section
(Section 11.10.5.5 “USB Control register
11.10.5.4). It can then write data
and
Section 11.16 “Double
Section 11.15.3
Table
UM10360
(Table
© NXP B.V. 2010. All rights reserved.
250) command.
215). When
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