LPC1769FBD100,551 NXP Semiconductors, LPC1769FBD100,551 Datasheet - Page 46
LPC1769FBD100,551
Manufacturer Part Number
LPC1769FBD100,551
Description
IC ARM CORTEX MCU 512K 100-LQFP
Manufacturer
NXP Semiconductors
Series
LPC17xxr
Datasheets
1.OM11043.pdf
(79 pages)
2.LPC1767FBD100551.pdf
(2 pages)
3.LPC1767FBD100551.pdf
(840 pages)
4.LPC1769FBD100551.pdf
(66 pages)
Specifications of LPC1769FBD100,551
Program Memory Type
FLASH
Program Memory Size
512KB (512K x 8)
Package / Case
100-LQFP
Core Processor
ARM® Cortex-M3™
Core Size
32-Bit
Speed
120MHz
Connectivity
CAN, Ethernet, I²C, IrDA, Microwire, SPI, SSI, UART/USART, USB OTG
Peripherals
Brown-out Detect/Reset, DMA, I²S, Motor Control PWM, POR, PWM, WDT
Number Of I /o
70
Ram Size
64K x 8
Voltage - Supply (vcc/vdd)
2.4 V ~ 3.6 V
Data Converters
A/D 8x12b, D/A 1x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Processor Series
LPC17
Core
ARM Cortex M3
Data Bus Width
32 bit
Data Ram Size
64 KB
Interface Type
Ethernet, USB, OTG, CAN
Maximum Clock Frequency
120 MHz
Number Of Programmable I/os
70
Number Of Timers
4
Operating Supply Voltage
3.3 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
MDK-ARM, RL-ARM, ULINK2, MCB1760, MCB1760U, MCB1760UME
Minimum Operating Temperature
- 40 C
On-chip Adc
12 bit, 8 Channel
On-chip Dac
10 bit
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
622-1005 - USB IN-CIRCUIT PROG ARM7 LPC2K
Eeprom Size
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Other names
568-4966
935290522551
935290522551
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
LPC1769FBD100,551
Manufacturer:
NXP Semiconductors
Quantity:
10 000
- OM11043 PDF datasheet
- LPC1767FBD100551 PDF datasheet #2
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- LPC1769FBD100551 PDF datasheet #4
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NXP Semiconductors
UM10360
User manual
4.5.13 PLL0 setup sequence
The following sequence must be followed step by step in order to have PLL0 initialized
and running:
It is very important not to merge any steps above. For example, do not update the
PLL0CFG and enable PLL0 simultaneously with the same feed sequence.
1. Disconnect PLL0 with one feed sequence if PLL0 is already connected.
2. Disable PLL0 with one feed sequence.
3. Change the CPU Clock Divider setting to speed up operation without PLL0, if desired.
4. Write to the Clock Source Selection Control register to change the clock source if
5. Write to the PLL0CFG and make it effective with one feed sequence. The PLL0CFG
6. Enable PLL0 with one feed sequence.
7. Change the CPU Clock Divider setting for the operation with PLL0. It is critical to do
8. Wait for PLL0 to achieve lock by monitoring the PLOCK0 bit in the PLL0STAT register,
9. Connect PLL0 with one feed sequence.
needed.
can only be updated when PLL0 is disabled.
this before connecting PLL0.
or using the PLOCK0 interrupt, or wait for a fixed time when the input clock to PLL0 is
slow (i.e. 32 kHz). The value of PLOCK0 may not be stable when the PLL reference
frequency (FREF, the frequency of REFCLK, which is equal to the PLL input
frequency divided by the pre-divider value) is less than 100 kHz or greater than
20 MHz. In these cases, the PLL may be assumed to be stable after a start-up time
has passed. This time is 500 µs when FREF is greater than 400 kHz and 200 / FREF
seconds when FREF is less than 400 kHz.
All information provided in this document is subject to legal disclaimers.
Rev. 2 — 19 August 2010
Chapter 4: LPC17xx Clocking and power control
UM10360
© NXP B.V. 2010. All rights reserved.
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