LPC1769FBD100,551 NXP Semiconductors, LPC1769FBD100,551 Datasheet - Page 277

• Manufacturer Part Number: LPC1769FBD100,551
• Description: IC ARM CORTEX MCU 512K 100-LQFP
• Manufacturer: NXP Semiconductors
• Series: LPC17xxr

Specifications of LPC1769FBD100,551

• Program Memory Type: FLASH
• Program Memory Size: 512KB (512K x 8)
• Package / Case: 100-LQFP
• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 120MHz
• Connectivity: CAN, Ethernet, I²C, IrDA, Microwire, SPI, SSI, UART/USART, USB OTG
• Peripherals: Brown-out Detect/Reset, DMA, I²S, Motor Control PWM, POR, PWM, WDT
• Number Of I /o: 70
• Ram Size: 64K x 8
• Voltage - Supply (vcc/vdd): 2.4 V ~ 3.6 V
• Data Converters: A/D 8x12b, D/A 1x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Processor Series: LPC17
• Core: ARM Cortex M3
• Data Bus Width: 32 bit
• Data Ram Size: 64 KB
• Interface Type: Ethernet, USB, OTG, CAN
• Maximum Clock Frequency: 120 MHz
• Number Of Programmable I/os: 70
• Number Of Timers: 4
• Operating Supply Voltage: 3.3 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2, MCB1760, MCB1760U, MCB1760UME
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 12 bit, 8 Channel
• On-chip Dac: 10 bit
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 622-1005 - USB IN-CIRCUIT PROG ARM7 LPC2K
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 568-4966; 935290522551

NXP Semiconductors
13.8 Register description
UM10360
User manual
13.8.1 USB Interrupt Status Register (USBIntSt - 0x5000 C1C0)
The OTG and I
The Device and Host registers are explained in
Device Controller and USB Host (OHCI) Controller chapters. All registers are 32 bits wide
and aligned to word address boundaries.
Table 256. USB OTG and I
The USB OTG controller has seven interrupt lines. This register allows software to
determine their status with a single read operation.
The interrupt lines are ORed together to a single channel of the vectored interrupt
controller.
Remark: In a device-only configuration bits 6 to 3 of this register are reserved (see
Table
Table 257. USB Interrupt Status register - (USBIntSt - address 0x5000 C1C0) bit description
Name
Interrupt register
USBIntSt
OTG registers
OTGIntSt
OTGIntEn
OTGIntSet
OTGIntClr
OTGStCtrl
OTGTmr
I
I2C_RX
I2C_TX
I2C_STS
I2C_CTL
I2C_CLKHI
I2C_CLKLO
Clock control registers
OTGClkCtrl
OTGClkSt
Bit
0
1
2
3
2
C registers
191).
Symbol
USB_INT_REQ_LP
USB_INT_REQ_HP
USB_INT_REQ_DMA
USB_HOST_INT
2
All information provided in this document is subject to legal disclaimers.
C registers are summarized in the following table.
Description
USB Interrupt Status
OTG Interrupt Status
OTG Interrupt Enable
OTG Interrupt Set
OTG Interrupt Clear
OTG Status and Control
OTG Timer
I
I
I
I
I
I
OTG clock controller
OTG clock status
2
2
2
2
2
2
C Receive
C Transmit
C Status
C Control
C Clock High
C Clock Low
Rev. 2 — 19 August 2010
2
C register address definitions
Description
Low priority interrupt line status. This bit is read-only.
High priority interrupt line status. This bit is read-only.
DMA interrupt line status. This bit is read-only.
USB host interrupt line status. This bit is read-only.
Table 254
R/W
Access Reset value
R/W
RO
R/W
WO
WO
R/W
R/W
RO
WO
RO
R/W
R/W
WO
RO
Chapter 13: LPC17xx USB OTG
and
0x8000 0100
0
0
NA
NA
0
0
0xFFFF
NA
NA
0x0A00
0
0xB9
0xB9
0
Table 188
UM10360
© NXP B.V. 2010. All rights reserved.
in the USB
Address
0x400F C1C0
0x5000 C100
0x5000 C104
0x5000 C108
0x5000 C10C
0x5000 C110
0x5000 C114
0x5000 C300
0x5000 C300
0x5000 C304
0x5000 C308
0x5000 C30C
0x5000 C310
0x5000 CFF4
0x5000 CFF8
277 of 840
0
0
Reset
Value
0
0