LPC1769FBD100,551 NXP Semiconductors, LPC1769FBD100,551 Datasheet - Page 447

• Manufacturer Part Number: LPC1769FBD100,551
• Description: IC ARM CORTEX MCU 512K 100-LQFP
• Manufacturer: NXP Semiconductors
• Series: LPC17xxr

Specifications of LPC1769FBD100,551

• Program Memory Type: FLASH
• Program Memory Size: 512KB (512K x 8)
• Package / Case: 100-LQFP
• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 120MHz
• Connectivity: CAN, Ethernet, I²C, IrDA, Microwire, SPI, SSI, UART/USART, USB OTG
• Peripherals: Brown-out Detect/Reset, DMA, I²S, Motor Control PWM, POR, PWM, WDT
• Number Of I /o: 70
• Ram Size: 64K x 8
• Voltage - Supply (vcc/vdd): 2.4 V ~ 3.6 V
• Data Converters: A/D 8x12b, D/A 1x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Processor Series: LPC17
• Core: ARM Cortex M3
• Data Bus Width: 32 bit
• Data Ram Size: 64 KB
• Interface Type: Ethernet, USB, OTG, CAN
• Maximum Clock Frequency: 120 MHz
• Number Of Programmable I/os: 70
• Number Of Timers: 4
• Operating Supply Voltage: 3.3 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2, MCB1760, MCB1760U, MCB1760UME
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 12 bit, 8 Channel
• On-chip Dac: 10 bit
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 622-1005 - USB IN-CIRCUIT PROG ARM7 LPC2K
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 568-4966; 935290522551

NXP Semiconductors
UM10360
User manual
19.8.10 I
19.8.8 I
19.8.9 I
0x4001 C0[30, 34, 38, 3C]; I
0x4005 C0[30, 34, 38, 3C]; I
0x400A 00[30, 34, 38, 3C])
The four mask registers each contain seven active bits (7:1). Any bit in these registers
which is set to ‘1’ will cause an automatic compare on the corresponding bit of the
received address when it is compared to the I2ADRn register associated with that mask
register. In other words, bits in an I2ADRn register which are masked are not taken into
account in determining an address match.
The mask register has no effect on comparison to the General Call address (“0000000”).
When an address-match interrupt occurs, the processor will have to read the data register
(I2DAT) to determine which received address actually caused the match.
Table 391. I
0x4001 C010; I
0x400A 0010)
Table 392. I
0x4001 C014; I
0x400A 0014)
Table 393. I
Bit
0
7:1
31:8
Bit
15:0
31:16 -
Bit
15:0
31:16 -
2
2
2
C Mask registers (I2MASK0 to 3: I
C SCL HIGH duty cycle register (I2SCLH: I
C SCL Low duty cycle register (I2SCLL: I
Symbol Description
-
MASK
-
Symbol Description
SCLH
Symbol Description
SCLL
38, 3C]; I
I2C2MASK[0, 1, 2, 3] - address 0x400A 00[30, 34, 38, 3C]) bit description
0x4001 C010; I
0x400A 0010) bit description
I2C1SCLL: 0x4005 C014; I
2
2
2
C Mask registers (I2MASK0 to 3: I
C SCL HIGH Duty Cycle register (I2SCLH: I
C SCL Low duty cycle register (I2SCLL: I
All information provided in this document is subject to legal disclaimers.
Reserved. User software should not write ones to reserved bits. This bit
reads always back as 0.
Mask bits.
Reserved. User software should not write ones to reserved bits. These
bits read always back as zeroes.
Count for SCL HIGH time period selection.
Reserved. The value read from a reserved bit is not defined.
Count for SCL low time period selection.
Reserved. The value read from a reserved bit is not defined.
2
2
2
C1, I2C1SCLH - 0x4005 C010; I
C1 - I2C1SCLL: 0x4005 C014; I
C1, I2C1MASK[0, 1, 2, 3] - address 0x4005 C0[30, 34, 38, 3C]; I
Rev. 2 — 19 August 2010
2
C1, I2C1SCLH - address 0x4005 C010; I
2
2
C1, I2C1MASK[0, 1, 2, 3] - address
C2, I2C2MASK[0, 1, 2, 3] - address
2
C2 - I2C2SCLL: 0x400A 0014) bit description
2
2
C0, I2C0MASK[0, 1, 2, 3] - 0x4001 C0[30, 34,
C0, I2C0MASK[0, 1, 2, 3] -
2
C0 - I2C0SCLL: 0x4001 C014; I
2
C0, I2C0SCLH - address
2
C0 - I2C0SCLL:
2
C0, I2C0SCLH -
Chapter 19: LPC17xx I2C0/1/2
2
2
C2 - I2C2SCLL:
C2, I2C2SCLH -
2
C2, I2C2SCLH -
UM10360
© NXP B.V. 2010. All rights reserved.
NA
NA
Reset value
0x0004
Reset value
0x0004
2
C2,
447 of 840
2
C1 -
Reset
value
0
0x00
0