LPC1769FBD100,551 NXP Semiconductors, LPC1769FBD100,551 Datasheet - Page 803

• Manufacturer Part Number: LPC1769FBD100,551
• Description: IC ARM CORTEX MCU 512K 100-LQFP
• Manufacturer: NXP Semiconductors
• Series: LPC17xxr

Specifications of LPC1769FBD100,551

• Program Memory Type: FLASH
• Program Memory Size: 512KB (512K x 8)
• Package / Case: 100-LQFP
• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 120MHz
• Connectivity: CAN, Ethernet, I²C, IrDA, Microwire, SPI, SSI, UART/USART, USB OTG
• Peripherals: Brown-out Detect/Reset, DMA, I²S, Motor Control PWM, POR, PWM, WDT
• Number Of I /o: 70
• Ram Size: 64K x 8
• Voltage - Supply (vcc/vdd): 2.4 V ~ 3.6 V
• Data Converters: A/D 8x12b, D/A 1x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Processor Series: LPC17
• Core: ARM Cortex M3
• Data Bus Width: 32 bit
• Data Ram Size: 64 KB
• Interface Type: Ethernet, USB, OTG, CAN
• Maximum Clock Frequency: 120 MHz
• Number Of Programmable I/os: 70
• Number Of Timers: 4
• Operating Supply Voltage: 3.3 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2, MCB1760, MCB1760U, MCB1760UME
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 12 bit, 8 Channel
• On-chip Dac: 10 bit
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 622-1005 - USB IN-CIRCUIT PROG ARM7 LPC2K
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 568-4966; 935290522551

NXP Semiconductors
35.3 Tables
Table 1.
Table 2.
Table 3.
Table 4.
Table 5.
Table 6.
Table 7.
Table 8.
Table 9.
Table 10. External Interrupt Flag register (EXTINT - address
Table 11. External Interrupt Mode register (EXTMODE -
Table 12. External Interrupt Polarity register (EXTPOLAR -
Table 13. System Controls and Status register (SCS -
Table 14. Summary of system control registers . . . . . . . .30
Table 15. Recommended values for C
Table 16. Recommended values for C
Table 17. Clock Source Select register (CLKSRCSEL -
Table 18. PLL0 registers . . . . . . . . . . . . . . . . . . . . . . . . .36
Table 19. PLL Control register (PLL0CON - address
Table 20. PLL0 Configuration register (PLL0CFG - address
Table 21. Multiplier values for PLL0 with a 32 kHz input .38
Table 22. PLL Status register (PLL0STAT - address
Table 23. PLL control bit combinations . . . . . . . . . . . . . .40
Table 24. PLL Feed register (PLL0FEED - address
Table 25. PLL frequency parameter . . . . . . . . . . . . . . . . .41
Table 26. Additional Multiplier Values for use with a Low
Table 27. Summary of PLL0 examples . . . . . . . . . . . . . .43
Table 28. Potential values for PLL example . . . . . . . . . . .45
Table 29. PLL1 registers . . . . . . . . . . . . . . . . . . . . . . . . .47
Table 30. PLL1 Control register (PLL1CON - address
Table 31. PLL Configuration register (PLL1CFG - address
Table 32. PLL1 Status register (PLL1STAT - address
Table 33. PLL1 control bit combinations . . . . . . . . . . . . .50
Table 34. PLL1 Feed register (PLL1FEED - address
Table 35. Elements determining PLL frequency. . . . . . . .52
UM10360
User manual
Ordering information . . . . . . . . . . . . . . . . . . . . .7
Ordering options for LPC17xx parts . . . . . . . . . .7
LPC17xx memory usage and details . . . . . . . .12
APB0 peripherals and base addresses . . . . . .14
APB1 peripherals and base addresses . . . . . .15
Pin summary. . . . . . . . . . . . . . . . . . . . . . . . . . .17
Summary of system control registers . . . . . . . .18
Reset Source Identification register (RSID -
address 0x400F C180) bit description . . . . . . .21
External Interrupt registers . . . . . . . . . . . . . . . .24
0x400F C140) bit description . . . . . . . . . . . . . .25
address 0x400F C148) bit description . . . . . . .26
address 0x400F C14C) bit description . . . . . . .26
address 0x400F C1A0) bit description . . . . . . .28
mode (crystal and external components
parameters) low frequency mode (OSCRANGE =
0, see
mode (crystal and external components
parameters) high frequency mode (OSCRANGE =
1, see
address 0x400F C10C) bit description . . . . . . .34
0x400F C080) bit description . . . . . . . . . . . . . .37
0x400F C084) bit description . . . . . . . . . . . . . .37
0x400F C088) bit description . . . . . . . . . . . . . .39
0x400F C08C) bit description . . . . . . . . . . . . . .40
Frequency Clock Input . . . . . . . . . . . . . . . . . . .42
0x400F C0A0) bit description . . . . . . . . . . . . . .49
0x400F C0A4) bit description . . . . . . . . . . . . . .49
0x400F C0A8) bit description . . . . . . . . . . . . . .50
0x400F C0AC) bit description. . . . . . . . . . . . . .51
Table
Table
13) . . . . . . . . . . . . . . . . . . . . . . . .32
13) . . . . . . . . . . . . . . . . . . . . . . . .32
X1/X2
X1/X2
All information provided in this document is subject to legal disclaimers.
in oscillation
in oscillation
Rev. 2 — 19 August 2010
Table 36. PLL1 Divider values . . . . . . . . . . . . . . . . . . . . 53
Table 37. PLL1 Multiplier values . . . . . . . . . . . . . . . . . . . 53
Table 38. CPU Clock Configuration register (CCLKCFG -
Table 39. USB Clock Configuration register (USBCLKCFG -
Table 40. Peripheral Clock Selection register 0 (PCLKSEL0
Table 41. Peripheral Clock Selection register 1 (PCLKSEL1
Table 42. Peripheral Clock Selection register bit values . 57
Table 43. Power Control registers . . . . . . . . . . . . . . . . . . 60
Table 44. Power Mode Control register (PCON - address
Table 45. Encoding of reduced power modes . . . . . . . . . 62
Table 46. Power Control for Peripherals register (PCONP -
Table 47. Clock Output Configuration register
Table 48. Summary of flash accelerator registers . . . . . . 69
Table 49. Flash Accelerator Configuration register
Table 50. Connection of interrupt sources to the Vectored
Table 51. NVIC register map . . . . . . . . . . . . . . . . . . . . . 76
Table 52. Interrupt Set-Enable Register 0 register (ISER0 -
Table 53. Interrupt Set-Enable Register 1 register (ISER1 -
Table 54. Interrupt Clear-Enable Register 0 (ICER0 -
Table 55. Interrupt Clear-Enable Register 1 register (ICER1
Table 56. Interrupt Set-Pending Register 0 register (ISPR0 -
Table 57. Interrupt Set-Pending Register 1 register (ISPR1 -
Table 58. Interrupt Clear-Pending Register 0 register
Table 59. Interrupt Set-Pending Register 1 register (ISPR1 -
Table 60. Interrupt Active Bit Register 0 (IABR0 - 0xE000
Table 61. Interrupt Active Bit Register 1 (IABR1 - 0xE000
Table 62. Interrupt Priority Register 0 (IPR0 - 0xE000
Table 63. Interrupt Priority Register 1 (IPR1 - 0xE000
Table 64. Interrupt Priority Register 2 (IPR2 - 0xE000
Table 65. Interrupt Priority Register 3 (IPR3 - 0xE000
Table 66. Interrupt Priority Register 4 (IPR4 - 0xE000
address 0x400F C104) bit description . . . . . . . 55
address 0x400F C108) bit description . . . . . . . 56
- address 0x400F C1A8) bit description. . . . . . 56
- address 0x400F C1AC) bit description . . . . . 57
0x400F C0C0) bit description . . . . . . . . . . . . . 61
address 0x400F C0C4) bit description. . . . . . . 63
(CLKOUTCFG - 0x400F C1C8) bit description 66
(FLASHCFG - address 0x400F C000) bit
description . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
Interrupt Controller . . . . . . . . . . . . . . . . . . . . . . 73
0xE000 E100) . . . . . . . . . . . . . . . . . . . . . . . . . 77
0xE000 E104) . . . . . . . . . . . . . . . . . . . . . . . . . 78
0xE000 E180) . . . . . . . . . . . . . . . . . . . . . . . . . 79
- 0xE000 E184) . . . . . . . . . . . . . . . . . . . . . . . . 80
0xE000 E200) . . . . . . . . . . . . . . . . . . . . . . . . . 81
0xE000 E204) . . . . . . . . . . . . . . . . . . . . . . . . . 82
(ICPR0 - 0xE000 E280) . . . . . . . . . . . . . . . . . 83
0xE000 E204) . . . . . . . . . . . . . . . . . . . . . . . . . 84
E300) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85
E304) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86
E400) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87
E404) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87
E408) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87
E40C) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88
E410) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88
Chapter 35: Supplementary information
UM10360
© NXP B.V. 2010. All rights reserved.
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