LPC1769FBD100,551 NXP Semiconductors, LPC1769FBD100,551 Datasheet - Page 213

• Manufacturer Part Number: LPC1769FBD100,551
• Description: IC ARM CORTEX MCU 512K 100-LQFP
• Manufacturer: NXP Semiconductors
• Series: LPC17xxr

Specifications of LPC1769FBD100,551

• Program Memory Type: FLASH
• Program Memory Size: 512KB (512K x 8)
• Package / Case: 100-LQFP
• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 120MHz
• Connectivity: CAN, Ethernet, I²C, IrDA, Microwire, SPI, SSI, UART/USART, USB OTG
• Peripherals: Brown-out Detect/Reset, DMA, I²S, Motor Control PWM, POR, PWM, WDT
• Number Of I /o: 70
• Ram Size: 64K x 8
• Voltage - Supply (vcc/vdd): 2.4 V ~ 3.6 V
• Data Converters: A/D 8x12b, D/A 1x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Processor Series: LPC17
• Core: ARM Cortex M3
• Data Bus Width: 32 bit
• Data Ram Size: 64 KB
• Interface Type: Ethernet, USB, OTG, CAN
• Maximum Clock Frequency: 120 MHz
• Number Of Programmable I/os: 70
• Number Of Timers: 4
• Operating Supply Voltage: 3.3 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2, MCB1760, MCB1760U, MCB1760UME
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 12 bit, 8 Channel
• On-chip Dac: 10 bit
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 622-1005 - USB IN-CIRCUIT PROG ARM7 LPC2K
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 568-4966; 935290522551

11.1 How to read this chapter
11.2 Basic configuration
11.3 Introduction
UM10360
User manual
This chapter describes the USB controller which is present on all LPC17xx devices except
the LPC1767. On some LPC17xx family devices, the USB controller can also be
configured for Host or OTG operation.
The USB controller is configured using the following registers:
The Universal Serial Bus (USB) is a four-wire bus that supports communication between a
host and one or more (up to 127) peripherals. The host controller allocates the USB
bandwidth to attached devices through a token-based protocol. The bus supports hot
plugging and dynamic configuration of the devices. All transactions are initiated by the
host controller.
The host schedules transactions in 1 ms frames. Each frame contains a Start-Of-Frame
(SOF) marker and transactions that transfer data to or from device endpoints. Each device
can have a maximum of 16 logical or 32 physical endpoints. There are four types of
transfers defined for the endpoints. Control transfers are used to configure the device.
Interrupt transfers are used for periodic data transfer. Bulk transfers are used when the
rate of transfer is not critical. Isochronous transfers have guaranteed delivery time but no
error correction.
For more information on the Universal Serial Bus, see the USB Implementers Forum
website.
The USB device controller on the LPC17xx enables full-speed (12 Mb/s) data exchange
with a USB host controller.
1. Power: In the PCONP register
2. Clock: The USB block can be used with a dedicated USB PLL (PLL1) to obtain the
3. Pins: Select USB pins and their modes in PINSEL0 to PINSEL5 and PINMODE0 to
4. Wake-up: Activity on the USB bus port can wake up the microcontroller from
5. Interrupts: Interrupts are enabled in the NVIC using the appropriate Interrupt Set
6. Initialization: see
UM10360
Chapter 11: LPC17xx USB device controller
Rev. 2 — 19 August 2010
Remark: On reset, the USB block is disabled (PCUSB = 0).
USB clock or with the Main PLL (PLL0). See
PINMODE5
Power-down mode, see
Enable register.
All information provided in this document is subject to legal disclaimers.
(Section
Section
Rev. 2 — 19 August 2010
8.5).
Section
11.13.
(Table
4.8.8.
46), set bit PCUSB.
Section
4.6.1.
© NXP B.V. 2010. All rights reserved.
User manual
213 of 840