LPC1769FBD100,551 NXP Semiconductors, LPC1769FBD100,551 Datasheet - Page 123

• Manufacturer Part Number: LPC1769FBD100,551
• Description: IC ARM CORTEX MCU 512K 100-LQFP
• Manufacturer: NXP Semiconductors
• Series: LPC17xxr

Specifications of LPC1769FBD100,551

• Program Memory Type: FLASH
• Program Memory Size: 512KB (512K x 8)
• Package / Case: 100-LQFP
• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 120MHz
• Connectivity: CAN, Ethernet, I²C, IrDA, Microwire, SPI, SSI, UART/USART, USB OTG
• Peripherals: Brown-out Detect/Reset, DMA, I²S, Motor Control PWM, POR, PWM, WDT
• Number Of I /o: 70
• Ram Size: 64K x 8
• Voltage - Supply (vcc/vdd): 2.4 V ~ 3.6 V
• Data Converters: A/D 8x12b, D/A 1x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Processor Series: LPC17
• Core: ARM Cortex M3
• Data Bus Width: 32 bit
• Data Ram Size: 64 KB
• Interface Type: Ethernet, USB, OTG, CAN
• Maximum Clock Frequency: 120 MHz
• Number Of Programmable I/os: 70
• Number Of Timers: 4
• Operating Supply Voltage: 3.3 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2, MCB1760, MCB1760U, MCB1760UME
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 12 bit, 8 Channel
• On-chip Dac: 10 bit
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 622-1005 - USB IN-CIRCUIT PROG ARM7 LPC2K
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 568-4966; 935290522551

NXP Semiconductors
Table 102. GPIO interrupt register map
[1]
UM10360
User manual
Generic
Name
IntEnR
IntEnF
IntStatR
IntStatF
IntClr
IntStatus
Reset value reflects the data stored in used bits only. It does not include reserved bits content.
Description
GPIO Interrupt Enable for Rising edge.
GPIO Interrupt Enable for Falling edge.
GPIO Interrupt Status for Rising edge.
GPIO Interrupt Status for Falling edge.
GPIO Interrupt Clear.
GPIO overall Interrupt Status.
9.5.1 GPIO port Direction register FIOxDIR (FIO0DIR to FIO4DIR- 0x2009
C000 to 0x2009 C080)
This word accessible register is used to control the direction of the pins when they are
configured as GPIO port pins. Direction bit for any pin must be set according to the pin
functionality.
Note that GPIO pins P0.29 and P0.30 are shared with the USB_D+ and USB_D- pins and
must have the same direction. If either FIO0DIR bit 29 or 30 are configured as zero, both
P0.29 and P0.30 will be inputs. If both FIO0DIR bits 29 and 30 are ones, both P0.29 and
P0.30 will be outputs.
Table 103. Fast GPIO port Direction register FIO0DIR to FIO4DIR - addresses 0x2009 C000 to
Aside from the 32-bit long and word only accessible FIODIR register, every fast GPIO port
can also be controlled via several byte and half-word accessible registers listed in
Table
additional registers allow easier and faster access to the physical port pins.
Bit
31:0
104, too. Next to providing the same functions as the FIODIR register, these
Symbol
FIO0DIR
FIO1DIR
FIO2DIR
FIO3DIR
FIO4DIR
0x2009 C080) bit description
All information provided in this document is subject to legal disclaimers.
Value Description
0
1
Rev. 2 — 19 August 2010
Fast GPIO Direction PORTx control bits. Bit 0 in FIOxDIR
controls pin Px.0, bit 31 in FIOxDIR controls pin Px.31.
Controlled pin is input.
Controlled pin is output.
Chapter 9: LPC17xx General Purpose Input/Output (GPIO)
Access Reset
R/W
R/W
RO
RO
WO
RO
value
0
0
0
0
0
0
[1]
PORTn Register
Name & Address
IO0IntEnR - 0x4002 8090
IO2IntEnR - 0x4002 80B0
IO0IntEnR - 0x4002 8094
IO2IntEnR - 0x4002 80B4
IO0IntStatR - 0x4002 8084
IO2IntStatR - 0x4002 80A4
IO0IntStatF - 0x4002 8088
IO2IntStatF - 0x4002 80A8
IO0IntClr - 0x4002 808C
IO2IntClr - 0x4002 80AC
IOIntStatus - 0x4002 8080
UM10360
© NXP B.V. 2010. All rights reserved.
123 of 840
Reset
value
0x0