LPC1769FBD100,551 NXP Semiconductors, LPC1769FBD100,551 Datasheet - Page 373

• Manufacturer Part Number: LPC1769FBD100,551
• Description: IC ARM CORTEX MCU 512K 100-LQFP
• Manufacturer: NXP Semiconductors
• Series: LPC17xxr

Specifications of LPC1769FBD100,551

• Program Memory Type: FLASH
• Program Memory Size: 512KB (512K x 8)
• Package / Case: 100-LQFP
• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 120MHz
• Connectivity: CAN, Ethernet, I²C, IrDA, Microwire, SPI, SSI, UART/USART, USB OTG
• Peripherals: Brown-out Detect/Reset, DMA, I²S, Motor Control PWM, POR, PWM, WDT
• Number Of I /o: 70
• Ram Size: 64K x 8
• Voltage - Supply (vcc/vdd): 2.4 V ~ 3.6 V
• Data Converters: A/D 8x12b, D/A 1x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Processor Series: LPC17
• Core: ARM Cortex M3
• Data Bus Width: 32 bit
• Data Ram Size: 64 KB
• Interface Type: Ethernet, USB, OTG, CAN
• Maximum Clock Frequency: 120 MHz
• Number Of Programmable I/os: 70
• Number Of Timers: 4
• Operating Supply Voltage: 3.3 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2, MCB1760, MCB1760U, MCB1760UME
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 12 bit, 8 Channel
• On-chip Dac: 10 bit
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 622-1005 - USB IN-CIRCUIT PROG ARM7 LPC2K
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 568-4966; 935290522551

NXP Semiconductors
Table 339. Central Miscellaneous Status Register (CANMSR - address 0x4004 0008) bit description
16.10 Global acceptance filter
16.11 Acceptance filter modes
UM10360
User manual
Bit
0
1
7:2
8
9
31:10 -
Symbol
E1
E2
-
BS1
BS2
16.9.3 Central Miscellaneous Status Register (CANMSR - 0x4004 0008)
Description
When 1, one or both of the CAN1 Tx and Rx Error Counters has reached the limit set in the
CAN1EWL register (same as ES in CAN1GSR)
When 1, one or both of the CAN2 Tx and Rx Error Counters has reached the limit set in the
CAN2EWL register (same as ES in CAN2GSR)
Reserved, user software should not write ones to reserved bits. The value read from a
reserved bit is not defined.
When 1, the CAN1 controller is currently involved in bus activities (same as BS in
CAN1GSR).
When 1, the CAN2 controller is currently involved in bus activities (same as BS in
CAN2GSR).
Reserved, the value read from a reserved bit is not defined.
This block provides lookup for received Identifiers (called Acceptance Filtering in CAN
terminology) for all the CAN Controllers. It includes a 512 × 32 (2 kB) RAM in which
software maintains one to five tables of Identifiers. This RAM can contain up to 1024
Standard Identifiers or 512 Extended Identifiers, or a mixture of both types.
The Acceptance Filter can be put into different modes by setting the according AccOff,
AccBP, and eFCAN bits in the Acceptance Filter Mode Register
“Acceptance Filter Mode Register (AFMR - 0x4003
access to the Configuration Register and the ID Look-up table is handled differently.
Table 340. Acceptance filter modes and access control
[1]
[2]
A write access to all section configuration registers is only possible during the Acceptance
Filter Off and Bypass Mode. Read access is allowed in all Acceptance Filter Modes.
Acceptance
filter mode
Off Mode
Bypass
Mode
Operating
Mode and
FullCAN
Mode
The whole ID Look-up Table RAM is only word accessible.
During the Operating Mode of the Acceptance Filter the Look-up Table can be accessed only to disable or
enable Messages.
Bit
AccOff
1
X
0
All information provided in this document is subject to legal disclaimers.
Bit
AccBP
0
1
0
Rev. 2 — 19 August 2010
Acceptance
filter state
reset &
halted
reset &
halted
running
ID Look-up
table
RAM
r/w access
from CPU
r/w access
from CPU
read-only
from CPU
[1]
C000)”). During each mode the
[2]
Acceptanc
e filter
config.
registers
r/w access
from CPU
r/w access
from CPU
access from
Acceptance
filter only
Chapter 16: LPC17xx CAN1/2
(Section 16.14.1
CAN controller
message receive
interrupt
no messages
accepted
all messages
accepted
hardware
acceptance filtering
UM10360
© NXP B.V. 2010. All rights reserved.
Reset Value
0
0
NA
0
0
NA
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