DF2117VLP20V Renesas Electronics America, DF2117VLP20V Datasheet - Page 210

IC H8S/2117 MCU FLASH 145TFLGA

DF2117VLP20V

Manufacturer Part Number
DF2117VLP20V
Description
IC H8S/2117 MCU FLASH 145TFLGA
Manufacturer
Renesas Electronics America
Series
H8® H8S/2100r
Datasheet

Specifications of DF2117VLP20V

Core Processor
H8S/2600
Core Size
16-Bit
Speed
20MHz
Connectivity
FIFO, I²C, LPC, SCI, SmartCard
Peripherals
POR, PWM, WDT
Number Of I /o
112
Program Memory Size
160KB (160K x 8)
Program Memory Type
FLASH
Ram Size
8K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 16x10b
Oscillator Type
External
Operating Temperature
-20°C ~ 75°C
Package / Case
145-TFLGA
For Use With
HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)3DK2166 - DEV EVAL KIT H8S/2166
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
DF2117VLP20V
Manufacturer:
Renesas
Quantity:
100
Part Number:
DF2117VLP20V
Manufacturer:
RENESAS/瑞萨
Quantity:
20 000
Section 7 I/O Ports
(3)
The pin function is switched as shown below according to the combination of the register setting
of the SCI and the P84DDR bit.
Module
Name
SCI
I/O port
(4)
The pin function is switched as shown below according to the combination of the SCIFE bit in
HICR5 and the LPC4E bit in HICR4 of the LPC, LPC3E to LPC1E bits in HICR0, and the
P83DDR bit. LPCENABLE in the following table is expressed by the following logical
expression.
LPCENABLE = 1 : SCIFE + LPC4E + LPC3E + LPC2E + LPC1E
Module
Name
LPC
I/O port
Rev. 3.00 Sep. 28, 2009 Page 164 of 910
REJ09B0350-0300
P84/IRQ3/TxD1
P83/LPCPD
Pin Function
P84 input
(initial setting)
Pin Function
LPCPD input
P83 input
(initial setting)
TxD1 output
P84 output
P83 output
SCI
TxD1_OE
1
0
0
Logical Expression
LPCENABLE
1
0
0
Setting
Setting
I/O Port
P84DDR
1
0
I/O Port
P83DDR
1
0

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