DF2117VLP20V Renesas Electronics America, DF2117VLP20V Datasheet - Page 522

• Manufacturer Part Number: DF2117VLP20V
• Description: IC H8S/2117 MCU FLASH 145TFLGA
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2100r

Specifications of DF2117VLP20V

• Core Processor: H8S/2600
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: FIFO, I²C, LPC, SCI, SmartCard
• Peripherals: POR, PWM, WDT
• Number Of I /o: 112
• Program Memory Size: 160KB (160K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 16x10b
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 145-TFLGA
• For Use With: HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)3DK2166 - DEV EVAL KIT H8S/2166
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

Section 16 Serial Communication Interface with FIFO (SCIF)
16.3.8
FFCR is a write-only register that controls transmit/receive FIFOs.
Rev. 3.00 Sep. 28, 2009 Page 476 of 910
REJ09B0350-0300
Bit
7
6
5, 4
3
2
1
0
Bit Name
RCVRTRIG1
RCVRTRIG0
–
DMAMODE
XMITFRST
RCVRFRST
FIFOE
FIFO Control Register (FFCR)
Initial Value R/W
0
0
⎯
0
0
0
0
W
W
⎯
⎯
W
W
W
Description
Receive FIFO Interrupt Trigger Level 1, 0
These bits set the trigger level of the receive FIFO
interrupt.
00: 1 byte
01: 4 bytes
10: 8 bytes
11: 14 bytes
Reserved
These bits cannot be modified.
DMA Mode
This bit is not supported and cannot be modified.
Transmit FIFO Reset
The transmit FIFO data is cleared when 1 is written.
However, FTSR data is not cleared. This bit is
automatically cleared.
Receive FIFO Reset
The receive FIFO data is cleared when 1 is written.
However, FRSR data is not cleared.
This bit is automatically cleared.
FIFO Enable
0: Transmit/receive FIFOs disabled
1: Transmit/receive FIFOs enabled
All bytes of these FIFOs are cleared.