DF2117VLP20V Renesas Electronics America, DF2117VLP20V Datasheet - Page 275

• Manufacturer Part Number: DF2117VLP20V
• Description: IC H8S/2117 MCU FLASH 145TFLGA
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2100r

Specifications of DF2117VLP20V

• Core Processor: H8S/2600
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: FIFO, I²C, LPC, SCI, SmartCard
• Peripherals: POR, PWM, WDT
• Number Of I /o: 112
• Program Memory Size: 160KB (160K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 16x10b
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 145-TFLGA
• For Use With: HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)3DK2166 - DEV EVAL KIT H8S/2166
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

9.5
A PWM waveform like the one shown in figure 9.3 is output from the PWMX pin. DA13 to DA0
in DADR corresponds to the total width (T
(256 pulses when CFS = 0, 64 pulses when CFS = 1). When OS = 0, this waveform is directly
output. When OS = 1, the output waveform is inverted, and DA13 to DA0 in DADR value
corresponds to the total width (T
types of waveform output available.
Table 9.5 summarizes the relationships between the CKS and CFS bit settings and the resolution,
base cycle, and conversion cycle. The PWM output remains fixed unless DA13 to DA0 in DADR
contain at least a certain minimum value. The relationship between the OS bit and the output
waveform is shown in figures 9.4 and 9.5.
Operation
Base cycle
(T × 64 or T × 256)
t
L
t
f
Figure 9.3 PWMX (D/A) Operation
H
) of the high (1) output pulses. Figures 9.4 and 9.5 show the
L
(T × 2
) of the low (0) pulses output in one conversion cycle
1 conversion cycle
14
(= 16384))
T: Resolution
T
(When CFS = 0, m = 256
When CFS = 1, m = 64)
Rev. 3.00 Sep. 28, 2009 Page 229 of 910
L
= Σ t
n = 1
m
Section 9 14-Bit PWM Timer (PWMX)
Ln
(OS = 0)
REJ09B0350-0300