DF2117VLP20V Renesas Electronics America, DF2117VLP20V Datasheet - Page 588

• Manufacturer Part Number: DF2117VLP20V
• Description: IC H8S/2117 MCU FLASH 145TFLGA
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2100r

Specifications of DF2117VLP20V

• Core Processor: H8S/2600
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: FIFO, I²C, LPC, SCI, SmartCard
• Peripherals: POR, PWM, WDT
• Number Of I /o: 112
• Program Memory Size: 160KB (160K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 16x10b
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 145-TFLGA
• For Use With: HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)3DK2166 - DEV EVAL KIT H8S/2166
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

Section 17 I
The master mode reception procedure and operations are described below.
1. Clear the TRS bit in ICCR to 0 to switch from transmit mode to receive mode.
2. When ICDR is read (dummy data read), reception is started, the receive clock is output in
3. The master device drives SDA low to return the acknowledge data at the 9th receive clock
4. Clear the IRIC flag to determine the next interrupt.
5. Read ICDR receive data. This clears the ICDRF flag to 0. The master device outputs the
Data can be received continuously by repeating steps [3] to [5].
6. Set the ACKB bit to 1 so as to return the acknowledge data for the last reception.
7. Read ICDR receive data. This clears the ICDRF flag to 0. The master device outputs the
8. When one frame of data has been received, the ICDRF, IRIC, and IRTR flags are set to 1 at the
9. Clear the IRIC flag to 0.
10. Read ICDR receive data after setting the TRS bit. This clears the ICDRF flag to 0.
11. Clear the BBSY bit and SCP bit to 0 in ICCR. This changes SDA from low to high when SCL
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Clear the ACKB bit in ICSR to 0 (acknowledge data setting).
Clear the IRIC flag to 0 to determine the end of reception.
Go to step [6] to halt reception operation if the first frame is the last receive data.
synchronization with the internal clock, and data is received. (Data from the SDA pin is
sequentially transferred to ICDRS in synchronization with the rise of the receive clock pulses.)
pulse. The receive data is transferred from ICDRS to ICDRR at the rise of the 9th clock pulse,
setting the ICDRF, IRIC, and IRTR flags to 1. If the IEIC bit has been set to 1, an interrupt
request is sent to the CPU.
The master device drives SCL low from the fall of the 9th receive clock pulse to the ICDR data
reading.
Go to step [6] to halt reception operation if the next frame is the last receive data.
receive clock continuously to receive the next data.
receive clock to receive data.
rise of the 9th receive clock pulse.
is high, and generates the stop condition.
2
C Bus Interface (IIC)