DF2117VLP20V Renesas Electronics America, DF2117VLP20V Datasheet - Page 840

• Manufacturer Part Number: DF2117VLP20V
• Description: IC H8S/2117 MCU FLASH 145TFLGA
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2100r

Specifications of DF2117VLP20V

• Core Processor: H8S/2600
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: FIFO, I²C, LPC, SCI, SmartCard
• Peripherals: POR, PWM, WDT
• Number Of I /o: 112
• Program Memory Size: 160KB (160K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 16x10b
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 145-TFLGA
• For Use With: HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)3DK2166 - DEV EVAL KIT H8S/2166
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

Section 25 List of Registers
Rev. 3.00 Sep. 28, 2009 Page 794 of 910
REJ09B0350-0300
Register Name
Port C input data register
Port C data direction register
Port D input data register
Port D data direction register
Timer control register_0
Timer mode register_0
Timer I/O control register H_0
Timer I/O control register L_0
Timer interrupt enable register_0
Timer status register_0
Timer counter _0
Timer general register A_0
Timer general register B_0
Timer general register C_0
Timer general register D_0
Timer control register_2
Timer mode register_2
Timer I/O control register_2
Timer interrupt enable register_2
Timer status register_2
Timer counter _2
Timer general register A_2
Timer general register B_2
System control register 3
Module stop control register A
Module stop control register B
Keyboard matrix interrupt register
Abbreviation
PCPIN
PCDDR
PDPIN
PDDDR
TCR_0
TMDR_0
TIORH_0
TIORL_0
TIER_0
TSR_0
TCNT_0
TGRA_0
TGRB_0
TGRC_0
TGRD_0
TCR_2
TMDR_2
TIOR_2
TIER_2
TSR_2
TCNT_2
TGRA_2
TGRB_2
SYSCR3
MSTPCRA
MSTPCRB
KMIMR
Number
of bits
8
8
8
8
8
8
8
8
8
8
16
16
16
16
16
8
8
8
8
8
16
16
16
8
8
8
8
Address
H'FE4E (Read)
(PORTS = 0)
H'FE4E (Write)
(PORTS = 0)
H'FE4F (Read)
(PORTS = 0)
H'FE4F (Write)
(PORTS = 0)
H'FE53
H'FE56
H'FE58
H'FE5A
H'FE76
H'FE78
H'FE7A
H'FE7D
H'FE7E
H'FE81
(RELOCATE = 1)
H'FE50
H'FE51
H'FE52
H'FE54
H'FE55
H'FE5C
H'FE5E
H'FE70
H'FE71
H'FE72
H'FE74
H'FE75
H'FE7F
Module
PORT
PORT
PORT
PORT
TPU_0
TPU_0
TPU_0
TPU_0
TPU_0
TPU_0
TPU_0
TPU_0
TPU_0
TPU_0
TPU_0
TPU_2
TPU_2
TPU_2
TPU_2
TPU_2
TPU_2
TPU_2
TPU_2
SYSTEM 8
SYSTEM 8
SYSTEM 8
INT
Data
Width
8
8
8
8
8
8
8
8
8
8
16
16
16
16
16
8
8
8
8
8
16
16
16
8
Access
States
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2