DF2117VLP20V Renesas Electronics America, DF2117VLP20V Datasheet - Page 832

• Manufacturer Part Number: DF2117VLP20V
• Description: IC H8S/2117 MCU FLASH 145TFLGA
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2100r

Specifications of DF2117VLP20V

• Core Processor: H8S/2600
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: FIFO, I²C, LPC, SCI, SmartCard
• Peripherals: POR, PWM, WDT
• Number Of I /o: 112
• Program Memory Size: 160KB (160K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 16x10b
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 145-TFLGA
• For Use With: HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)3DK2166 - DEV EVAL KIT H8S/2166
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

Section 25 List of Registers
Rev. 3.00 Sep. 28, 2009 Page 786 of 910
REJ09B0350-0300
Register Name
Port G noise cancel cycle setting
register
Port I data direction register
Port J data direction register
Port I output data register
Port J output data register
Port I input data register
Port J input data register
Port J pull-up MOS control register
Port I Nch-OD control register
Port J Nch-OD control register
TDP timer counter_0
TDP pulse width upper limit
register_0
TDP pulse width lower limit
register_0
TDP cycle upper limit register_0
TDP input capture register_0
TDP input capture buffer register_0
TDP status register_0
TDP control register 1_0
TDP interrupt enable register_0
TDP control register 2_0
TDP cycle lower limit register_0
TDP timer counter_1
TDP pulse width upper limit
register_1
TDP pulse width lower limit
register_1
TDP cycle upper limit register_1
TDP input capture register_1
TDP input capture buffer register_1
TDP status register_1
Abbreviation
PGNCCS
PIDDR
PJDDR
PIODR
PJODR
PIPIN
PJPIN
PJPCR
PINOCR
PJNOCR
TDPCNT_0
TDPWDMX_0 16
TDPWDMN_0 16
TDPPDMX_0
TDPICR_0
TDPICRF_0
TDPCSR_0
TDPCR1_0
TDPIER_0
TDPCR2_0
TDPPDMN_0
TDPCNT_1
TDPWDMX_1 16
TDPWDMN_1 16
TDPPDMX_1
TDPICR_1
TDPICRF_1
TDPCSR_1
Number
of bits
8
8
8
8
8
8
8
8
8
8
16
16
16
16
8
8
8
8
16
16
16
16
16
8
Address
H'F98E
(PORTS = 1)
H'F990
H'F991
H'F992
H'F993
H'F994 (Read)
H'F995 (Read)
H'F997
H'F998
H'F999
H'FB40
H'FB42
H'FB44
H'FB46
H'FB48
H'FB4A
H'FB4C
H'FB4D
H'FB4E
H'FB50
H'FB60
H'FB62
H'FB64
H'FB66
H'FB68
H'FB6A
H'FB6C
H'FB4F
Module
PORT
PORT
TDP_0
TDP_0
TDP_0
TDP_0
TDP_1
TDP_1
PORT
PORT
PORT
PORT
PORT
PORT
PORT
PORT
TDP_0
TDP_0
TDP_0
TDP_0
TDP_0
TDP_0
TDP_0
TDP_1
TDP_1
TDP_1
TDP_1
TDP_1
Data
Width
8
8
8
8
8
8
8
8
8
8
16
16
16
16
16
16
8
8
8
8
16
16
16
16
16
16
16
8
Access
States
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2