DF2117VLP20V Renesas Electronics America, DF2117VLP20V Datasheet - Page 37

• Manufacturer Part Number: DF2117VLP20V
• Description: IC H8S/2117 MCU FLASH 145TFLGA
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2100r

Specifications of DF2117VLP20V

• Core Processor: H8S/2600
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: FIFO, I²C, LPC, SCI, SmartCard
• Peripherals: POR, PWM, WDT
• Number Of I /o: 112
• Program Memory Size: 160KB (160K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 16x10b
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 145-TFLGA
• For Use With: HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)3DK2166 - DEV EVAL KIT H8S/2166
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

11.4 Operation ........................................................................................................................... 317
11.5 Interrupt Sources................................................................................................................ 324
11.6 Usage Notes ....................................................................................................................... 325
Section 12 16-Bit Duty Period Measurement Timer (TDP) ..............................329
12.1 Features.............................................................................................................................. 329
12.2 Input/Output Pins ............................................................................................................... 331
12.3 Register Descriptions ......................................................................................................... 332
12.4 Operation ........................................................................................................................... 344
12.5 Interrupt Sources................................................................................................................ 351
11.3.3 TCM Cycle Lower Limit Register (TCMMINCM) .............................................. 310
11.3.4 TCM Input Capture Register (TCMICR).............................................................. 310
11.3.5 TCM Input Capture Buffer Register (TCMICRF) ................................................ 310
11.3.6 TCM Status Register (TCMCSR) ......................................................................... 311
11.3.7 TCM Control Register (TCMCR)......................................................................... 313
11.3.8 TCM Interrupt Enable Register (TCMIER) .......................................................... 315
11.4.1 Timer Mode .......................................................................................................... 317
11.4.2 Cycle Measurement Mode .................................................................................... 319
11.6.1 Conflict between TCMCNT Write and Count-Up Operation ............................... 325
11.6.2 Conflict between TCMMLCM Write and Compare Match.................................. 325
11.6.3 Conflict between TCMICR Read and Input Capture ............................................ 326
11.6.4 Conflict between Edge Detection in Cycle Measurement Mode and
11.6.5 Conflict between Edge Detection in Cycle Measurement Mode and
11.6.6 Settings of TCMCKI and TCMMCI ..................................................................... 327
11.6.7 Setting for Module Stop Mode.............................................................................. 327
12.3.1 TDP Timer Counter (TDPCNT) ........................................................................... 333
12.3.2 TDP Pulse Width Upper Limit Register (TDPWDMX) ....................................... 334
12.3.3 TDP Pulse Width Lower Limit Register (TDPWDMN)....................................... 334
12.3.4 TDP Cycle Upper Limit Register (TDPPDMX) ................................................... 334
12.3.5 TDP Cycle Lower Limit Register (TDPPDMN)................................................... 335
12.3.6 TDP Input Capture Register (TDPICR) ................................................................ 335
12.3.7 TDP Input Capture Buffer Register (TDPICRF) .................................................. 335
12.3.8 TDP Status Register (TDPCSR) ........................................................................... 335
12.3.9 TDP Control Register 1 (TDPCR1) ...................................................................... 338
12.3.10 TDP Control Register 2 (TDPCR2) ...................................................................... 341
12.3.11 TDP Interrupt Enable Register (TDPIER) ............................................................ 342
12.4.1 Timer Mode .......................................................................................................... 344
12.4.2 Cycle Measurement Mode .................................................................................... 346
Writing to TCMMLCM or TCMMINCM ............................................................ 326
Clearing of TCMMDS Bit in TCMCR ................................................................. 327
Rev. 3.00 Sep. 28, 2009 Page xxxv of xliv
REJ09B0350-0300