DF2117VLP20V Renesas Electronics America, DF2117VLP20V Datasheet - Page 523

• Manufacturer Part Number: DF2117VLP20V
• Description: IC H8S/2117 MCU FLASH 145TFLGA
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2100r

Specifications of DF2117VLP20V

• Core Processor: H8S/2600
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: FIFO, I²C, LPC, SCI, SmartCard
• Peripherals: POR, PWM, WDT
• Number Of I /o: 112
• Program Memory Size: 160KB (160K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 16x10b
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 145-TFLGA
• For Use With: HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)3DK2166 - DEV EVAL KIT H8S/2166
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

16.3.9
FLCR sets formats of the transmit/receive data.
Bit
7
6
5
4
3
Bit Name
DLAB
BREAK
STICK
PARITY
EPS
PEN
Line Control Register (FLCR)
Initial Value
0
0
0
0
0
R/W
R/W
R/W
R
R/W
R/W
Section 16 Serial Communication Interface with FIFO (SCIF)
Description
Divisor Latch Address
FDLL and FDLH are placed at the same addresses
as the FRBR/FTHR and FIER addresses. This bit
selects which register is to be accessed.
0: FRBR/FTHR and FIER access enabled
1: FDLL and FDLH access enabled
Break Control
Generates a break by driving the serial output signal
FTxD low.
The break state is released by clearing this bit.
0: Break released
1: Break generated
Stick Parity
These bits are not supported in this LSI.
These bits are always read as 0 and cannot be
modified.
Parity Select
Selects even or odd parity when the PEN bit is 1.
0: Odd parity
1: Even parity
Parity Enable
Selects whether to add a parity bit for data
transmission and whether to perform a parity check
for data reception.
0: No parity bit added/parity check disabled
1: Parity bit added/parity check enabled
Rev. 3.00 Sep. 28, 2009 Page 477 of 910
REJ09B0350-0300