DF2117VLP20V Renesas Electronics America, DF2117VLP20V Datasheet - Page 411

• Manufacturer Part Number: DF2117VLP20V
• Description: IC H8S/2117 MCU FLASH 145TFLGA
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2100r

Specifications of DF2117VLP20V

• Core Processor: H8S/2600
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: FIFO, I²C, LPC, SCI, SmartCard
• Peripherals: POR, PWM, WDT
• Number Of I /o: 112
• Program Memory Size: 160KB (160K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 16x10b
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 145-TFLGA
• For Use With: HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)3DK2166 - DEV EVAL KIT H8S/2166
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

Note:
[Legend]
x:
⎯:
Channel CKS2
TMR_X
* If the TMR_Y clock input is set as the TCNT_X overflow signal and the TMR_X clock
Don't care
Invalid
0
0
0
0
1
0
0
0
0
1
1
1
1
input is set as the TCNT_Y compare-match signal simultaneously, a count-up clock
cannot be generated. These settings should not be made.
CKS1
0
0
1
1
0
0
0
1
1
0
0
1
1
TCR
CKS0
0
1
0
1
0
0
1
0
1
0
1
0
1
CKSX
0
0
0
0
0
1
1
1
1
1
x
x
x
TCRXY
—
—
—
—
CKSY
—
—
—
—
—
—
—
—
—
Description
Increments at φ
Increments at φ/2
Increments at φ/4
Increments at φ/2048
Increments at φ/4096
Increments at φ/8192
Increments at compare-match A from
TCNT_Y*
Increments at rising edge of external
clock
Increments at falling edge of external
clock
Increments at both rising and falling
edges of external clock
Disables clock input
Disables clock input
Disables clock input
Rev. 3.00 Sep. 28, 2009 Page 365 of 910
Section 13 8-Bit Timer (TMR)
REJ09B0350-0300