DF2117VLP20V Renesas Electronics America, DF2117VLP20V Datasheet - Page 545

IC H8S/2117 MCU FLASH 145TFLGA

DF2117VLP20V

Manufacturer Part Number
DF2117VLP20V
Description
IC H8S/2117 MCU FLASH 145TFLGA
Manufacturer
Renesas Electronics America
Series
H8® H8S/2100r
Datasheet

Specifications of DF2117VLP20V

Core Processor
H8S/2600
Core Size
16-Bit
Speed
20MHz
Connectivity
FIFO, I²C, LPC, SCI, SmartCard
Peripherals
POR, PWM, WDT
Number Of I /o
112
Program Memory Size
160KB (160K x 8)
Program Memory Type
FLASH
Ram Size
8K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 16x10b
Oscillator Type
External
Operating Temperature
-20°C ~ 75°C
Package / Case
145-TFLGA
For Use With
HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)3DK2166 - DEV EVAL KIT H8S/2166
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
DF2117VLP20V
Manufacturer:
Renesas
Quantity:
100
Part Number:
DF2117VLP20V
Manufacturer:
RENESAS/瑞萨
Quantity:
20 000
16.4.5
As shown in table 16.3, setting the SCIFE bit in HICR5 to 1 allows registers (except SCIFCR) to
be accessed from the LPC interface. The initial setting of SCIFCR by the CPU and setting of the
SCIFE bit in HICR5 to 1 enable the flow settings for initialization and data transmission/reception
shown in figures 16.3 to 16.5 to be made from the LPC interface. Table 16.7 shows the
correspondence between LPC interface I/O address and access to the SCIF registers. For details of
the LPC interface settings, see section 19, LPC interface (LPC).
Table 16.7 Correspondence Between LPC Interface I/O Address and the SCIF Registers
Bits 15 to 3
SCIFADR (bits 15 to 3)
SCIFADR (bits 15 to 3)
SCIFADR (bits 15 to 3)
SCIFADR (bits 15 to 3)
SCIFADR (bits 15 to 3)
SCIFADR (bits 15 to 3)
SCIFADR (bits 15 to 3)
SCIFADR (bits 15 to 3)
Data Transmission/Reception Through the LPC Interface
LPC Interface I/O Address
Bit 2
0
0
0
0
1
1
1
1
Bit 1
0
0
1
1
0
0
1
1
Section 16 Serial Communication Interface with FIFO (SCIF)
Bit 0
0
1
0
1
0
1
0
1
R/W
R
W
R/W
R/W
R/W
R
W
R/W
R/W
R
R
R/W
Rev. 3.00 Sep. 28, 2009 Page 499 of 910
Condition
FLCR[7] = 0
FLCR[7] = 0
FLCR[7] = 1
FLCR[7] = 0
FLCR[7] = 1
REJ09B0350-0300
SCIF
Register
FRBR
FTHR
FDLL
FIER
FDLH
FIIR
FFCR
FLCR
FMCR
FLSR
FMSR
FSCR

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