DF2117VLP20V Renesas Electronics America, DF2117VLP20V Datasheet - Page 400
DF2117VLP20V
Manufacturer Part Number
DF2117VLP20V
Description
IC H8S/2117 MCU FLASH 145TFLGA
Manufacturer
Renesas Electronics America
Series
H8® H8S/2100r
Datasheet
1.DF2117VBG20V.pdf
(960 pages)
Specifications of DF2117VLP20V
Core Processor
H8S/2600
Core Size
16-Bit
Speed
20MHz
Connectivity
FIFO, I²C, LPC, SCI, SmartCard
Peripherals
POR, PWM, WDT
Number Of I /o
112
Program Memory Size
160KB (160K x 8)
Program Memory Type
FLASH
Ram Size
8K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 16x10b
Oscillator Type
External
Operating Temperature
-20°C ~ 75°C
Package / Case
145-TFLGA
For Use With
HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)3DK2166 - DEV EVAL KIT H8S/2166
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Available stocks
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Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
DF2117VLP20V
Manufacturer:
Renesas
Quantity:
100
Part Number:
DF2117VLP20V
Manufacturer:
RENESAS/瑞萨
Quantity:
20 000
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Section 12 16-Bit Duty Period Measurement Timer (TDP)
12.6.5
When the TDPMDS bit in TDPCR1 is cleared in cycle measurement mode while the CST bit in
TDPCR1 is 1 and the edge of TDPCYI is detected at the same time, the detected edge signal will
cause the timer to continue to operate in cycle measurement mode. The timer enters timer mode
when the next edge is detected. Therefore, ensure that the CST bit is cleared to 0 in cycle
measurement mode.
Figure 12.17 shows the timing of this conflict.
12.6.6
TDPCKI and TDPMCI are multiplexed on the same pin of this LSI. Therefore, the selected
external clock and the TDPMCI signal cannot be used at the same time. Do not make the settings
CKS2 to CKS0 = B'111 and PMMS = B'1.
12.6.7
The module-stop control register can be used to specify whether to continue or stop TDP
operation. The default setting is for the TDP operation to stop. The TDP registers become
accessible on release from module stop mode. For details, see section 24, Power-Down Modes.
Rev. 3.00 Sep. 28, 2009 Page 354 of 910
REJ09B0350-0300
Figure 12.17 Conflict between Edge Detection and TDPMDS Bit Clearing (In Switching
φ
TDPCYI
Input capture
signal
Internal write
signal
TDPMDS
TDPCNT
TDPICR
Conflict between Edge Detection in Cycle Measurement Mode and TDPMDS Bit
Clearing
Settings for TDPCKI and TDPMCI
Setting for Module Stop Mode
from Cycle Measurement Mode to Timer Mode)
M
L
H'0000
TDPCNT cleared
at the first rising edge
M
N
TDPCNT is not cleared
N
N + 1
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