DF2117VLP20V Renesas Electronics America, DF2117VLP20V Datasheet - Page 670

• Manufacturer Part Number: DF2117VLP20V
• Description: IC H8S/2117 MCU FLASH 145TFLGA
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2100r

Specifications of DF2117VLP20V

• Core Processor: H8S/2600
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: FIFO, I²C, LPC, SCI, SmartCard
• Peripherals: POR, PWM, WDT
• Number Of I /o: 112
• Program Memory Size: 160KB (160K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 16x10b
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 145-TFLGA
• For Use With: HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)3DK2166 - DEV EVAL KIT H8S/2166
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

Section 19 LPC Interface (LPC)
19.3.14 SERIRQ Control Register 1 (SIRQCR1)
SIRQCR1 contains status bits that indicate the SERIRQ operating mode and bits that specify
SERIRQ interrupt sources.
Rev. 3.00 Sep. 28, 2009 Page 624 of 910
REJ09B0350-0300
Bit
7
6
IRQ11E3 0
IRQ10E3 0
Bit Name Initial Value Slave Host Description
R/W
R/W
R/W
⎯
⎯
Host IRQ11 Interrupt Enable 3
Enables or disables an HIRQ11 interrupt request
when OBF3A is set by an ODR3 write.
0: HIRQ11 interrupt request by OBF3A and
[Clearing conditions]
•
•
•
1: [When IEDIR3 = 0]
[Setting condition]
Writing 1 after reading IRQ11E3 = 0
Host IRQ10 Interrupt Enable 3
Enables or disables an HIRQ10 interrupt request
when OBF3A is set by an ODR3 write.
0: HIRQ10 interrupt request by OBF3A and
[Clearing conditions]
•
•
•
1: [When IEDIR3 = 0]
[Setting condition]
Writing 1 after reading IRQ10E3 = 0
IRQE11E3 is disabled
Writing 0 to IRQ11E3
LPC hardware reset, LPC software reset
Clearing OBF3A to 0 (when IEDIR3 = 0)
HIRQ11 interrupt request by setting OBF3A to 1
is enabled
[When IEDIR3 = 1]
HIRQ11 interrupt is requested
IRQE10E3 is disabled
Writing 0 to IRQ10E3
LPC hardware reset, LPC software reset
Clearing OBF3A to 0 (when IEDIR3 = 0)
HIRQ10 interrupt request by setting OBF3A to 1
is enabled
[When IEDIR3 = 1]
HIRQ10 interrupt is requested