DF2117VLP20V Renesas Electronics America, DF2117VLP20V Datasheet - Page 42

• Manufacturer Part Number: DF2117VLP20V
• Description: IC H8S/2117 MCU FLASH 145TFLGA
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2100r

Specifications of DF2117VLP20V

• Core Processor: H8S/2600
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: FIFO, I²C, LPC, SCI, SmartCard
• Peripherals: POR, PWM, WDT
• Number Of I /o: 112
• Program Memory Size: 160KB (160K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 16x10b
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 145-TFLGA
• For Use With: HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)3DK2166 - DEV EVAL KIT H8S/2166
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

17.4 Operation ........................................................................................................................... 534
17.5 Interrupt Sources................................................................................................................ 555
17.6 Usage Notes ....................................................................................................................... 555
Section 18 Keyboard Buffer Control Unit (PS2) ..............................................561
18.1 Features.............................................................................................................................. 561
18.2 Input/Output Pins............................................................................................................... 563
18.3 Register Descriptions ......................................................................................................... 564
18.4 Operation ........................................................................................................................... 573
Rev. 3.00 Sep. 28, 2009 Page xl of xliv
REJ09B0350-0300
17.3.5 I
17.3.6 I
17.3.7 I
17.3.8 I
17.4.1 I
17.4.2 Initialization.......................................................................................................... 536
17.4.3 Master Transmit Operation ................................................................................... 536
17.4.4 Master Receive Operation .................................................................................... 541
17.4.5 Slave Receive Operation....................................................................................... 544
17.4.6 Slave Transmit Operation ..................................................................................... 548
17.4.7 IRIC Setting Timing and SCL Control ................................................................. 551
17.4.8 Noise Canceller..................................................................................................... 553
17.4.9 Initialization of Internal State ............................................................................... 553
17.6.1 Module Stop Mode Setting ................................................................................... 559
18.3.1 Keyboard Control Register 1 (KBCR1)................................................................ 565
18.3.2 Keyboard Buffer Control Register 2 (KBCR2) .................................................... 567
18.3.3 Keyboard Control Register H (KBCRH) .............................................................. 568
18.3.4 Keyboard Control Register L (KBCRL) ............................................................... 570
18.3.5 Keyboard Data Buffer Register (KBBR) .............................................................. 572
18.3.6 Keyboard Buffer Transmit Data Register (KBTR) ............................................... 572
18.4.1 Receive Operation ................................................................................................ 573
18.4.2 Transmit Operation ............................................................................................... 575
18.4.3 Receive Abort ....................................................................................................... 576
18.4.4 KCLKI and KDI Read Timing ............................................................................. 579
18.4.5 KCLKO and KDO Write Timing ......................................................................... 579
18.4.6 KBF Setting Timing and KCLK Control.............................................................. 580
18.4.7 Receive Timing..................................................................................................... 581
18.4.8 Operation during Data Reception ......................................................................... 581
18.4.9 KCLK Fall Interrupt Operation ............................................................................ 582
18.4.10 First KCLK Falling Interrupt................................................................................ 583
2
2
2
2
2
C Bus Control Register (ICCR).......................................................................... 516
C Bus Status Register (ICSR)............................................................................. 525
C Bus Control Initialization Register (ICRES)................................................... 529
C Bus Extended Control Register (ICXR).......................................................... 530
C Bus Data Format ............................................................................................. 534