DF2117VLP20V Renesas Electronics America, DF2117VLP20V Datasheet - Page 293

• Manufacturer Part Number: DF2117VLP20V
• Description: IC H8S/2117 MCU FLASH 145TFLGA
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2100r

Specifications of DF2117VLP20V

• Core Processor: H8S/2600
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: FIFO, I²C, LPC, SCI, SmartCard
• Peripherals: POR, PWM, WDT
• Number Of I /o: 112
• Program Memory Size: 160KB (160K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 16x10b
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 145-TFLGA
• For Use With: HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)3DK2166 - DEV EVAL KIT H8S/2166
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

10.3.2
The TMDR registers are used to set the operating mode for each channel. The TPU has three
TMDR registers, one for each channel. TMDR register settings should be made only when TCNT
operation is stopped.
Bit
7
6
5
4
3
2
1
0
Bit Name
⎯
⎯
BFB
BFA
MD3
MD2
MD1
MD0
Timer Mode Register (TMDR)
Initial
value
1
1
0
0
0
0
0
0
R/W
R
R
R/W
R/W
R/W
R/W
R/W
R/W
Description
Reserved
These bits are always read as 1 and cannot be
modified.
Buffer Operation B
Specifies whether TGRB is to operate in the normal
way, or TGRB and TGRD are to be used together for
buffer operation. When TGRD is used as a buffer
register. TGRD input capture/output compare is not
generation. Because channels 1 and 2 have no TGRD,
bit 5 is reserved. It is always read as 0 and cannot be
modified.
0: TGRB operates normally
1: TGRB and TGRD used together for buffer operation
Buffer Operation A
Specifies whether TGRA is to operate in the normal
way, or TGRA and TGRC are to be used together for
buffer operation. When TGRC is used as a buffer
register, TGRC input capture/output compare is not
generated. Because channels 1 and 2 have no TGRC,
bit 4 is reserved. It is always read as 0 and cannot be
modified.
0: TGRA operates normally
1: TGRA and TGRC used together for buffer operation
Modes 3 to 0
These bits are used to set the timer operating mode.
MD3 is a reserved bit. In a write, the write value should
always be 0. See table 10.9 for details.
Rev. 3.00 Sep. 28, 2009 Page 247 of 910
Section 10 16-Bit Timer Pulse Unit (TPU)
REJ09B0350-0300