DF2117VLP20V Renesas Electronics America, DF2117VLP20V Datasheet - Page 227

• Manufacturer Part Number: DF2117VLP20V
• Description: IC H8S/2117 MCU FLASH 145TFLGA
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2100r

Specifications of DF2117VLP20V

• Core Processor: H8S/2600
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: FIFO, I²C, LPC, SCI, SmartCard
• Peripherals: POR, PWM, WDT
• Number Of I /o: 112
• Program Memory Size: 160KB (160K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 16x10b
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 145-TFLGA
• For Use With: HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)3DK2166 - DEV EVAL KIT H8S/2166
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

(3)
The pin function is switched as shown below according to the combination of the register setting
of PTCNT1 and the PG5DDR bit. When the ISS13 bit in ISSR16 is set to 1 and the IRQ13E bit in
IER16 of the interrupt controller is set to 1, this pin can be used as the ExIRQ13 input pin.
Module
Name
PTCNT1
I/O port
Note: The output format for ExSCLA is NMOS output only, and direct bus drive is possible. When
(4)
The pin function is switched as shown below according to the combination of the register setting
of PTCNT1 and the PG4DDR bit. When the ISS12 bit in ISSR16 is set to 1 and the IRQ12E bit in
IER16 of the interrupt controller is set to 1, this pin can be used as the ExIRQ12 input pin.
Module
Name
PTCNT1
I/O port
Note: The output format for ExSDAA is NMOS output only, and direct bus drive is possible. When
PG5/ExSCLA/ExIRQ13
PG4/ExSDAA/ExIRQ12
this pin is used as the PG5 output pin, the output format is NMOS push-pull.
this pin is used as the PG4 output pin, the output format is NMOS push-pull.
Pin Function
ExSCLA
input/output
PG5 output
PG5 input
(initial setting)
Pin Function
ExSDAA
input/output
PG4 output
PG4 input
(initial setting)
PTCNT1
ExSCLA_OE
1
0
0
PTCNT1
ExSDAA_OE
1
0
0
Rev. 3.00 Sep. 28, 2009 Page 181 of 910
Setting
Setting
I/O Port
PG5DDR
⎯
1
0
I/O Port
PG4DDR
⎯
1
0
Section 7 I/O Ports
REJ09B0350-0300