DF2117VLP20V Renesas Electronics America, DF2117VLP20V Datasheet - Page 482

• Manufacturer Part Number: DF2117VLP20V
• Description: IC H8S/2117 MCU FLASH 145TFLGA
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2100r

Specifications of DF2117VLP20V

• Core Processor: H8S/2600
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: FIFO, I²C, LPC, SCI, SmartCard
• Peripherals: POR, PWM, WDT
• Number Of I /o: 112
• Program Memory Size: 160KB (160K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 16x10b
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 145-TFLGA
• For Use With: HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)3DK2166 - DEV EVAL KIT H8S/2166
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

Section 15 Serial Communication Interface (SCI)
15.5.1
Figure 15.11 shows a sample flowchart for multiprocessor serial data transmission. For an ID
transmission cycle, set the MPBT bit in SSR to 1 before transmission. For a data transmission
cycle, clear the MPBT bit in SSR to 0 before transmission. All other SCI operations are the same
as those in asynchronous mode.
Rev. 3.00 Sep. 28, 2009 Page 436 of 910
REJ09B0350-0300
Multiprocessor Serial Data Transmission
Figure 15.11 Sample Multiprocessor Serial Transmission Flowchart
Clear DR to 0 and set DDR to 1
Write transmit data to TDR and
Read TDRE flag in SSR
Read TEND flag in SSR
Clear TE bit in SCR to 0
set MPBT bit in SSR
Clear TDRE flag to 0
All data transmitted?
Start transmission
End transmission
Break output?
Initialization
TDRE = 1
TEND = 1
Yes
Yes
Yes
Yes
No
No
No
No
[1]
[2]
[3]
[4]
[5]
[1] SCI initialization:
[2] SCI status check and transmit
[3] Serial transmission continuation
[4] Break output at the end of serial
Note:
The TxD pin is automatically
designated as the transmit data
output pin.
After the TE bit is set to 1, a
frame of 1s is output, and
transmission is enabled.
data write:
Read SSR and check that the
TDRE flag is set to 1, then write
transmit data to TDR. Set the
MPBT bit in SSR to 0 or 1.
Finally, clear the TDRE flag to
0.
procedure:
To continue serial transmission,
be sure to read 1 from the
TDRE flag to confirm that
writing is possible, then write
data to TDR, and then clear the
TDRE flag to 0.
transmission:
To output a break in serial
transmission, set port DDR to 1,
clear DR to 0, and then clear
the TE bit in SCR to 0.
Do not write to SMR, SCR,
BRR, and SDCR from the
start to the end of
transmission except the
process of [5].