DF2117VLP20V Renesas Electronics America, DF2117VLP20V Datasheet - Page 789

• Manufacturer Part Number: DF2117VLP20V
• Description: IC H8S/2117 MCU FLASH 145TFLGA
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2100r

Specifications of DF2117VLP20V

• Core Processor: H8S/2600
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: FIFO, I²C, LPC, SCI, SmartCard
• Peripherals: POR, PWM, WDT
• Number Of I /o: 112
• Program Memory Size: 160KB (160K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 16x10b
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 145-TFLGA
• For Use With: HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)3DK2166 - DEV EVAL KIT H8S/2166
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

The sequence of new bit-rate selection is shown in figure 22.21.
(5)
The boot program will transfer the erasing program and erase the data in the user MATs first , then
the data in the user boot MATs. On completion of this erasure, ACK will be returned and the
program will enter the programming/erasing state.
The host should select the device code, clock mode, and new bit rate with device selection, clock-
mode selection, and new bit-rate selection commands, and then send the command for the
transition to programming/erasing state. These procedures should be carried out before sending of
the programming selection command or program data.
Command
• Command, H'40, (one byte): Transition to programming/erasing state
Response
• Response, H'06, (one byte): Response to transition to programming/erasing state
Error Response
• Error response, H'C0, (one byte): Error response to the bland check of the user boot MATs
• Error code, H'51, (one byte): Erasing error
The boot program will send ACK when the user MATs and the user boot MATs have been
erased by the transferred erasing program.
An error occurred and erasure was not completed.
Transition to Programming/Erasing State
Waiting for one-bit period
at the specified bit rate
Setting a new bit rate
H'40
H'06
Host
H'C0
Figure 22.21 New Bit-Rate Selection Sequence
H'51
H'06 (ACK) with the new bit rate
H'06 (ACK) with the new bit rate
Setting a new bit rate
H'06 (ACK)
Rev. 3.00 Sep. 28, 2009 Page 743 of 910
Setting a new bit rate
Boot program
Section 22 Flash Memory
REJ09B0350-0300