DF2117VLP20V Renesas Electronics America, DF2117VLP20V Datasheet - Page 601

• Manufacturer Part Number: DF2117VLP20V
• Description: IC H8S/2117 MCU FLASH 145TFLGA
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2100r

Specifications of DF2117VLP20V

• Core Processor: H8S/2600
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: FIFO, I²C, LPC, SCI, SmartCard
• Peripherals: POR, PWM, WDT
• Number Of I /o: 112
• Program Memory Size: 160KB (160K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 16x10b
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 145-TFLGA
• For Use With: HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)3DK2166 - DEV EVAL KIT H8S/2166
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

17.5
The IIC has interrupt source IICI. Table 17.8 shows the interrupt sources and priority. Individual
interrupt sources can be enabled or disabled using the enable bits in ICCR, and are sent to the
interrupt controller independently.
The IIC interrupts are used as on-chip DTC activation sources.
Table 17.8 IIC Interrupt Sources
17.6
1. In master mode, if an instruction to generate a start condition is issued and then an instruction
2. Either of the following two conditions will start the next transfer. Pay attention to these
3. Table 17.9 shows the timing of SCL and SDA outputs in synchronization with the internal
Channel
0
1
2
to generate a stop condition is issued before the start condition is output to the I
condition will be output correctly.
conditions when accessing ICDR.
⎯ Write to ICDR when ICE = 1 and TRS = 1 (including automatic transfer from ICDRT to
⎯ Read from ICDR when ICE = 1 and TRS = 0 (including automatic transfer from ICDRS to
clock. Timings on the bus are determined by the rise and fall times of signals affected by the
bus load capacitance, series resistance, and parallel resistance.
ICDRS)
ICDRR)
Interrupt Sources
Usage Notes
Name
IICI0
IICI1
IICI2
Enable Bit
IEIC
IEIC
IEIC
Interrupt Source
I
request
I
request
I
request
2
2
2
C bus interface interrupt
C bus interface interrupt
C bus interface interrupt
Rev. 3.00 Sep. 28, 2009 Page 555 of 910
Section 17 I
Interrupt Flag Priority
IRIC
IRIC
IRIC
2
C Bus Interface (IIC)
REJ09B0350-0300
2
C bus, neither
High
Low