DF2117VLP20V Renesas Electronics America, DF2117VLP20V Datasheet - Page 214

IC H8S/2117 MCU FLASH 145TFLGA

DF2117VLP20V

Manufacturer Part Number
DF2117VLP20V
Description
IC H8S/2117 MCU FLASH 145TFLGA
Manufacturer
Renesas Electronics America
Series
H8® H8S/2100r
Datasheet

Specifications of DF2117VLP20V

Core Processor
H8S/2600
Core Size
16-Bit
Speed
20MHz
Connectivity
FIFO, I²C, LPC, SCI, SmartCard
Peripherals
POR, PWM, WDT
Number Of I /o
112
Program Memory Size
160KB (160K x 8)
Program Memory Type
FLASH
Ram Size
8K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 16x10b
Oscillator Type
External
Operating Temperature
-20°C ~ 75°C
Package / Case
145-TFLGA
For Use With
HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)3DK2166 - DEV EVAL KIT H8S/2166
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
DF2117VLP20V
Manufacturer:
Renesas
Quantity:
100
Part Number:
DF2117VLP20V
Manufacturer:
RENESAS/瑞萨
Quantity:
20 000
Section 7 I/O Ports
7.2.10
(1)
The pin function is switched according to the combination of the register setting of PS2 and the
PAnDDR bit. When the KMIMRm bit in KMIMRA of the interrupt controller is cleared to 0, this
pin can be used as the KINm input pin.
Module
Name
PS2
I/O port
Note: When the KBIOE bit is set to 1, this pin functions as an NMOS open-drain output, and direct
7.2.11
(1)
The pin function is switched as shown below according to the combination of the SCIFE bit in
HICR5 of LPC and the PB7DDR bit.
Module
Name
SCIF
I/O port
Rev. 3.00 Sep. 28, 2009 Page 168 of 910
REJ09B0350-0300
PA7/KIN15/PS2CD, PA6/KIN14/PS2CC, PA5/KIN13/PS2BD, PA4/KIN12/PS2BC,
PA3/KIN11/PS2AD, PA2/KIN10/PS2AC, PA1/KIN9/PS2DD, PA0/KIN8/PS2DC
PB7/RTS
bus drive is possible.
When the IICS bit in STCR is set to 1, the output format for PA7 to PA4 is NMOS open-
drain, and direct bus drive is possible.
Port A
Port B
Pin Function
PAn output
PAn input
(initial setting)
Pin Function
RTS output
PB7 output
PB7 input
(initial setting)
PS2 input/output
PS2
PS2_OE
1
0
SCIF
RTS_OE
1
0
0
0
Setting
Setting
I/O Port
PAnDDR
1
0
I/O Port
PB7DDR
1
0
(n = 7 to 0, m = 15 to 8)

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