DF2117VLP20V Renesas Electronics America, DF2117VLP20V Datasheet - Page 365

IC H8S/2117 MCU FLASH 145TFLGA

DF2117VLP20V

Manufacturer Part Number
DF2117VLP20V
Description
IC H8S/2117 MCU FLASH 145TFLGA
Manufacturer
Renesas Electronics America
Series
H8® H8S/2100r
Datasheet

Specifications of DF2117VLP20V

Core Processor
H8S/2600
Core Size
16-Bit
Speed
20MHz
Connectivity
FIFO, I²C, LPC, SCI, SmartCard
Peripherals
POR, PWM, WDT
Number Of I /o
112
Program Memory Size
160KB (160K x 8)
Program Memory Type
FLASH
Ram Size
8K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 16x10b
Oscillator Type
External
Operating Temperature
-20°C ~ 75°C
Package / Case
145-TFLGA
For Use With
HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)3DK2166 - DEV EVAL KIT H8S/2166
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
DF2117VLP20V
Manufacturer:
Renesas
Quantity:
100
Part Number:
DF2117VLP20V
Manufacturer:
RENESAS/瑞萨
Quantity:
20 000
(3)
The CMF flag in TCMCSR is set in the last state where the values in TCMCNT and TCMMLCM
match in timer mode. Therefore, a compare match signal is not generated until a further cycle of
the TCMCNT input clock is generated after a match between the values in TCMCNT and
TCMMLCM. For details, see section 11.6.2, Conflict between TCMMLCM Write and Compare
Match. Figure 11.6 shows the timing with which the CMF flag is set.
11.4.2
When the TCMMDS bit in TCMCR is set to 1, the TCM operates in cycle measurement mode.
(1)
Setting the TCMMDS bit in TCMCR to 1 selects cycle measurement mode, in which counting up
proceeds regardless of the setting of the CST bit in TCMCR. TCMCNT is cleared to H'0000 on
detection of the first edge in the measurement period and counts up from there. Figure 11.7 shows
an example of counter operation in cycle measurement mode.
CMF Set Timing when a Compare Match occurs
Counter Operation
φ
TCMCYI
TCMCNT
clear signal
TCMCNT
input clock
TCMCNT
φ
TCMCNT
TCMMLC
Compare match
signal
CMF
Cycle Measurement Mode
Figure 11.7 Example of Counter Operation in Cycle Measurement Mode
Figure 11.6 Timing of CMF Flag Setting on a Compare Match
N
H'0000
N
H'0001
Section 11 16-Bit Cycle Measurement Timer (TCM)
N
H'0002
Rev. 3.00 Sep. 28, 2009 Page 319 of 910
N + 1
H'0003
H'0000
REJ09B0350-0300
H'0001

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